[Intel-gfx] [PATCH v4] drm/i915: Apply Wa Display #1183 on skl, kbl, and cfl

Lucas De Marchi lucas.de.marchi at gmail.com
Thu Nov 16 02:31:13 UTC 2017


On Wed, Nov 15, 2017 at 6:26 PM, Lucas De Marchi
<lucas.demarchi at intel.com> wrote:
> Wa Display #1183 was recently added to workaround
> "Failures when enabling DPLL0 with eDP link rate 2.16
> or 4.32 GHz and CD clock frequency 308.57 or 617.14 MHz
> (CDCLK_CTL CD Frequency Select 10b or 11b) used in this
>  enabling or in previous enabling."
>
> This Workaround was designed to minimize the impact only
> to save the bad case with that link rates. But HW engineers
> indicated that it should be safe to apply broadly, although
> they were expecting the DPLL0 link rate to be unchanged on
> runtime.
>
> We need to cover 2 cases: when we are in fact enabling DPLL0
> and when we are just changing the frequency with small
> differences.
>
> This is based on previous patch by Rodrigo Vivi with suggestions
> from Ville Syrjälä.
>
> Cc: Arthur J Runyan <arthur.j.runyan at intel.com>
> Cc: Ville Syrjälä <ville.syrjala at linux.intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi at intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h         |  2 ++
>  drivers/gpu/drm/i915/intel_cdclk.c      | 44 +++++++++++++++++++++++----------
>  drivers/gpu/drm/i915/intel_runtime_pm.c | 10 ++++++++
>  3 files changed, 43 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index cfdf4f821ac3..b0a1bf5f549c 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7019,6 +7019,7 @@ enum {
>  #define  RESET_PCH_HANDSHAKE_ENABLE    (1<<4)
>
>  #define GEN8_CHICKEN_DCPR_1            _MMIO(0x46430)
> +#define   SKL_SELECT_ALTERNATE_DC_EXIT (1<<30)
>  #define   MASK_WAKEMEM                 (1<<13)
>
>  #define SKL_DFSM                       _MMIO(0x51000)
> @@ -8573,6 +8574,7 @@ enum skl_power_gate {
>  #define  BXT_CDCLK_CD2X_DIV_SEL_2      (2<<22)
>  #define  BXT_CDCLK_CD2X_DIV_SEL_4      (3<<22)
>  #define  BXT_CDCLK_CD2X_PIPE(pipe)     ((pipe)<<20)
> +#define  CDCLK_DIVMUX_CD_OVERRIDE      (1<<19)
>  #define  BXT_CDCLK_CD2X_PIPE_NONE      BXT_CDCLK_CD2X_PIPE(3)
>  #define  BXT_CDCLK_SSA_PRECHARGE_ENABLE        (1<<16)
>  #define  CDCLK_FREQ_DECIMAL_MASK       (0x7ff)
> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
> index e8884c2ade98..0a995c0f955e 100644
> --- a/drivers/gpu/drm/i915/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> @@ -931,16 +931,10 @@ static void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv,
>
>  static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
>  {
> -       int min_cdclk = skl_calc_cdclk(0, vco);
>         u32 val;
>
>         WARN_ON(vco != 8100000 && vco != 8640000);
>
> -       /* select the minimum CDCLK before enabling DPLL 0 */
> -       val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk);
> -       I915_WRITE(CDCLK_CTL, val);
> -       POSTING_READ(CDCLK_CTL);
> -
>         /*
>          * We always enable DPLL0 with the lowest link rate possible, but still
>          * taking into account the VCO required to operate the eDP panel at the
> @@ -994,7 +988,8 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv,
>  {
>         int cdclk = cdclk_state->cdclk;
>         int vco = cdclk_state->vco;
> -       u32 freq_select;
> +       u32 freq_select, cdclk_ctl;
> +       bool need_dpll0_enable;
>         int ret;
>
>         mutex_lock(&dev_priv->pcu_lock);
> @@ -1009,7 +1004,7 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv,
>                 return;
>         }
>
> -       /* set CDCLK_CTL */
> +       /* Choose frequency for this cdclk */
>         switch (cdclk) {
>         default:
>                 WARN_ON(cdclk != dev_priv->cdclk.hw.ref);
> @@ -1032,16 +1027,39 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv,
>                 break;
>         }
>
> -       if (dev_priv->cdclk.hw.vco != 0 &&
> -           dev_priv->cdclk.hw.vco != vco)
> +       need_dpll0_enable = dev_priv->cdclk.hw.vco != vco;
> +
> +       if (dev_priv->cdclk.hw.vco != 0 && need_dpll0_enable)
>                 skl_dpll0_disable(dev_priv);
>
> -       if (dev_priv->cdclk.hw.vco != vco)
> -               skl_dpll0_enable(dev_priv, vco);
> +       cdclk_ctl = I915_READ(CDCLK_CTL);
> +       cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);

Ooops,  this line should be inside the `if ()`  below... I fixed it up
and forgot it stashed.  I'll wait for a review before
resending.


Lucas De Marchi



>
> -       I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk));
> +       if (need_dpll0_enable) {
> +               /* Wa Display #1183: skl,kbl,cfl */
> +               cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
> +               I915_WRITE(CDCLK_CTL, cdclk_ctl);
> +       }
> +
> +       /* Wa Display #1183: skl,kbl,cfl */
> +       cdclk_ctl |= CDCLK_DIVMUX_CD_OVERRIDE;
> +       I915_WRITE(CDCLK_CTL, cdclk_ctl);
>         POSTING_READ(CDCLK_CTL);
>
> +       if (need_dpll0_enable)
> +               skl_dpll0_enable(dev_priv, vco);
> +
> +       /* Wa Display #1183: skl,kbl,cfl */
> +       cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
> +       I915_WRITE(CDCLK_CTL, cdclk_ctl);
> +
> +       cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
> +       I915_WRITE(CDCLK_CTL, cdclk_ctl);
> +
> +       /* Wa Display #1183: skl,kbl,cfl */
> +       cdclk_ctl &= ~CDCLK_DIVMUX_CD_OVERRIDE;
> +       I915_WRITE(CDCLK_CTL, cdclk_ctl);
> +
>         /* inform PCU of the change */
>         mutex_lock(&dev_priv->pcu_lock);
>         sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 8315499452dc..35796fa8e6b4 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -598,6 +598,11 @@ void gen9_enable_dc5(struct drm_i915_private *dev_priv)
>
>         DRM_DEBUG_KMS("Enabling DC5\n");
>
> +       /* Wa Display #1183: skl,kbl,cfl */
> +       if (IS_GEN9_BC(dev_priv))
> +               I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) |
> +                          SKL_SELECT_ALTERNATE_DC_EXIT);
> +
>         gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
>  }
>
> @@ -625,6 +630,11 @@ void skl_disable_dc6(struct drm_i915_private *dev_priv)
>  {
>         DRM_DEBUG_KMS("Disabling DC6\n");
>
> +       /* Wa Display #1183: skl,kbl,cfl */
> +       if (IS_GEN9_BC(dev_priv))
> +               I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) |
> +                          SKL_SELECT_ALTERNATE_DC_EXIT);
> +
>         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
>  }
>
> --
> 2.14.3
>
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-- 
Lucas De Marchi


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