[Intel-gfx] [PATCH 3/4] drm/i915: expose EU topology through sysfs

[Lionel Landwerlin]

On 17/11/17 10:53, Chris Wilson wrote:
> Quoting Lionel Landwerlin (2017-11-16 16:00:03)
>> With the introduction of asymetric slices in CNL, we cannot rely on
>> the previous SUBSLICE_MASK getparam. Here we introduce a more detailed
>> way of querying the Gen's GPU topology that doesn't aggregate numbers.
>>
>> This is essential for monitoring parts of the GPU with the OA unit,
>> because signals need to be accounted properly based on whether part of
>> the GPU has been fused off. The current aggregated numbers like
>> EU_TOTAL do not gives us sufficient information.
>>
>> Here is the sysfs layout on a Skylake GT4 :
>>
>> /sys/devices/pci0000:00/0000:00:02.0/drm/card0/topology/
> Ok, bikeshedding time!

Yey \o/

>
> We already use topology in conjunction with DP-MST, so at a toplevel
> this would be confusing.
>
> I would start with a gt/ dir for all of this info.

Fair.

>
> Is this subslicing only for the render unit; are all platforms going to
> have the same fusing across all units? At the least, I thought we would
> be able to configure the powergating of the different slices on the
> different units. It seems a logical extension that fusing would be
> similar.
> -Chris

I'm not quite sure what you're asking.

As far as I can see, the slice/subslice structure is here to stay.
What I read in the documentation is that we can set powergating at the 
slice level (since gen8) and at the subslice level (since gen10).
Are you thinking about allowing powergating configuration through sysfs? 
(I have no intention to add that at the moment).

-
Lionel