[Intel-gfx] [PATCH 1/3] drm/i915: Make ips_enabled a property depending on whether IPS is enabled.

[Maarten Lankhorst]

Op 20-11-17 om 11:58 schreef Ville Syrjälä:
> On Mon, Nov 20, 2017 at 11:48:22AM +0100, Maarten Lankhorst wrote:
>> Op 17-11-17 om 16:52 schreef Ville Syrjälä:
>>> On Fri, Nov 17, 2017 at 04:37:54PM +0100, Maarten Lankhorst wrote:
>>>> ips_enabled was used as a variable of whether IPS can be enabled or not,
>>>> but should be used to test whether IPS is actually enabled.
>>>>
>>>> Signed-off-by: Maarten Lankhorst <maarten.lankhorst at linux.intel.com>
>>>> ---
>>>>  drivers/gpu/drm/i915/intel_display.c  | 75 ++++++++++++++++-------------------
>>>>  drivers/gpu/drm/i915/intel_pipe_crc.c |  2 -
>>>>  2 files changed, 35 insertions(+), 42 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>>>> index 3b3dec1e6640..8283e80597bd 100644
>>>> --- a/drivers/gpu/drm/i915/intel_display.c
>>>> +++ b/drivers/gpu/drm/i915/intel_display.c
>>>> @@ -4870,7 +4870,7 @@ void hsw_enable_ips(const struct intel_crtc_state *crtc_state)
>>>>  	struct drm_device *dev = crtc->base.dev;
>>>>  	struct drm_i915_private *dev_priv = to_i915(dev);
>>>>  
>>>> -	if (!crtc->config->ips_enabled)
>>>> +	if (!crtc_state->ips_enabled)
>>>>  		return;
>>>>  
>>>>  	/*
>>>> @@ -4966,14 +4966,6 @@ intel_post_enable_primary(struct drm_crtc *crtc,
>>>>  	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>>>>  	int pipe = intel_crtc->pipe;
>>>>  
>>>> -	/*
>>>> -	 * FIXME IPS should be fine as long as one plane is
>>>> -	 * enabled, but in practice it seems to have problems
>>>> -	 * when going from primary only to sprite only and vice
>>>> -	 * versa.
>>>> -	 */
>>>> -	hsw_enable_ips(new_crtc_state);
>>>> -
>>>>  	/*
>>>>  	 * Gen2 reports pipe underruns whenever all planes are disabled.
>>>>  	 * So don't enable underrun reporting before at least some planes
>>>> @@ -4989,10 +4981,9 @@ intel_post_enable_primary(struct drm_crtc *crtc,
>>>>  	intel_check_pch_fifo_underruns(dev_priv);
>>>>  }
>>>>  
>>>> -/* FIXME move all this to pre_plane_update() with proper state tracking */
>>>> +/* FIXME get rid of this and use pre_plane_update */
>>>>  static void
>>>> -intel_pre_disable_primary(struct drm_crtc *crtc,
>>>> -			  const struct intel_crtc_state *old_crtc_state)
>>>> +intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
>>>>  {
>>>>  	struct drm_device *dev = crtc->dev;
>>>>  	struct drm_i915_private *dev_priv = to_i915(dev);
>>>> @@ -5001,32 +4992,12 @@ intel_pre_disable_primary(struct drm_crtc *crtc,
>>>>  
>>>>  	/*
>>>>  	 * Gen2 reports pipe underruns whenever all planes are disabled.
>>>> -	 * So diasble underrun reporting before all the planes get disabled.
>>>> -	 * FIXME: Need to fix the logic to work when we turn off all planes
>>>> -	 * but leave the pipe running.
>>>> +	 * So disable underrun reporting before all the planes get disabled.
>>>>  	 */
>>>>  	if (IS_GEN2(dev_priv))
>>>>  		intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
>>>>  
>>>> -	/*
>>>> -	 * FIXME IPS should be fine as long as one plane is
>>>> -	 * enabled, but in practice it seems to have problems
>>>> -	 * when going from primary only to sprite only and vice
>>>> -	 * versa.
>>>> -	 */
>>>> -	hsw_disable_ips(old_crtc_state);
>>>> -}
>>>> -
>>>> -/* FIXME get rid of this and use pre_plane_update */
>>>> -static void
>>>> -intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
>>>> -{
>>>> -	struct drm_device *dev = crtc->dev;
>>>> -	struct drm_i915_private *dev_priv = to_i915(dev);
>>>> -	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
>>>> -	int pipe = intel_crtc->pipe;
>>>> -
>>>> -	intel_pre_disable_primary(crtc, to_intel_crtc_state(crtc->state));
>>>> +	hsw_disable_ips(to_intel_crtc_state(crtc->state));
>>> BTW thinking about the lack of readout on BDW. In case the BIOS ever
>>> enables IPS, I think we should sanitize ips_enabled to true on BDW.
>>> Or maybe just have the redaout code always set ips_enabled=true on BDW?
>>> That way the first modeset will try to turn it off regardless of whether it
>>> was enabled or not.
>> Yes, good idea. :)
>>>>  
>>>>  	/*
>>>>  	 * Vblank time updates from the shadow to live plane control register
>>>> @@ -5058,6 +5029,11 @@ static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
>>>>  	if (pipe_config->update_wm_post && pipe_config->base.active)
>>>>  		intel_update_watermarks(crtc);
>>>>  
>>>> +	if (!old_crtc_state->ips_enabled ||
>>>> +	    needs_modeset(&old_crtc_state->base) ||
>>> Shoudldn't that be needs_modeset(new_crtc_state)?
>> Yes, oops..
>>>> +	    pipe_config->update_pipe)
>>> Why do we have to check that?
>> In case we take over the hw state from bios..
>>
>> If we default ips_enabled to true on BDW and read out on HSW again, then this
>> check will make IPS work, regardless of bios setting..
> Why aren't we just checking something like
> if ((!old_state->ips_enabled || needs_modeset()) && new_state->ips_enabled) ?
>
> IPS state may have to change whenever plane visibility changes, so I don't
> see any reson to involve ->update_pipe in these decision.
This is what we do, except the new_state->ips_enabled check is in hsw_enable_ips. We also allow update_pipe for broadwell, in which case we don't know the hw state.

~Maarten