[Intel-gfx] [PATCH igt 1/3] igt/perf_pmu: Idle the GPU before starting to measure busyness

[Tvrtko Ursulin]

On 22/11/2017 18:05, Chris Wilson wrote:
> Make sure the HW is idle before we start sampling the GPU for busyness.
> If we do not rest for long enough between tests, we may carry the
> sampling over.

Hm.. not sure about this one. New PMU client is supposed to start with a 
counter relative to the current value at counter enable. How did you 
come to this being a problem?

If I am missing something faster alternative would be to read the 
counter twice. But.. I don't think it should be necessary. I'll 
investigate tomorrow.

Regards,

Tvrtko

> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> Cc: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
> ---
>   tests/perf_pmu.c | 18 ++++++++++++++++++
>   1 file changed, 18 insertions(+)
> 
> diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
> index 8585ed7b..420eb6c9 100644
> --- a/tests/perf_pmu.c
> +++ b/tests/perf_pmu.c
> @@ -142,6 +142,9 @@ single(int gem_fd, const struct intel_execution_engine2 *e, bool busy)
>   	uint64_t val;
>   	int fd;
>   
> +	/* Ensure the HW is idle before being BUSY measurements */
> +	gem_quiescent_gpu(gem_fd);
> +
>   	fd = open_pmu(I915_PMU_ENGINE_BUSY(e->class, e->instance));
>   
>   	if (busy) {
> @@ -192,6 +195,9 @@ busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
>   	igt_spin_t *spin;
>   	unsigned int busy_idx, i;
>   
> +	/* Ensure the HW is idle before being BUSY measurements */
> +	gem_quiescent_gpu(gem_fd);
> +
>   	i = 0;
>   	fd[0] = -1;
>   	for_each_engine_class_instance(fd, e_) {
> @@ -237,6 +243,9 @@ most_busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
>   	igt_spin_t *spin[num_engines];
>   	unsigned int idle_idx, i;
>   
> +	/* Ensure the HW is idle before being BUSY measurements */
> +	gem_quiescent_gpu(gem_fd);
> +
>   	gem_require_engine(gem_fd, e->class, e->instance);
>   
>   	i = 0;
> @@ -292,6 +301,9 @@ all_busy_check_all(int gem_fd, const unsigned int num_engines)
>   	igt_spin_t *spin[num_engines];
>   	unsigned int i;
>   
> +	/* Ensure the HW is idle before being BUSY measurements */
> +	gem_quiescent_gpu(gem_fd);
> +
>   	i = 0;
>   	fd[0] = -1;
>   	for_each_engine_class_instance(fd, e) {
> @@ -628,6 +640,9 @@ multi_client(int gem_fd, const struct intel_execution_engine2 *e)
>   	uint64_t val[2];
>   	int fd[2];
>   
> +	/* Ensure the HW is idle before being BUSY measurements */
> +	gem_quiescent_gpu(gem_fd);
> +
>   	fd[0] = open_pmu(config);
>   
>   	/*
> @@ -742,6 +757,9 @@ static void cpu_hotplug(int gem_fd)
>   	uint64_t val, ref;
>   	int fd;
>   
> +	/* Ensure the HW is idle before being BUSY measurements */
> +	gem_quiescent_gpu(gem_fd);
> +
>   	igt_require(cpu0_hotplug_support());
>   
>   	fd = perf_i915_open(I915_PMU_ENGINE_BUSY(I915_ENGINE_CLASS_RENDER, 0));
>