[Intel-gfx] [PATCH] drm/i915/pmu: Aggregate all RC6 states into one counter

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursulin at intel.com>

Chris has discovered that RC6, RC6p and RC6pp counters are mutually
exclusive, and even that on some SNB SKUs you get RC6p increasing, and on
the others RC6.

Furthermore RC6p and RC6pp were only present starting from GEN6 until,
GEN7, not including Haswell.

All this combined makes it questionable whether we need to reserve new ABI
for these counters. One idea was to just combine them all under the RC6
counter to simplify things for userspace. So that is what this patch does.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
Suggested-by: Chris Wilson <chris at chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/i915_pmu.c | 23 ++++++-----------------
 include/uapi/drm/i915_drm.h     |  6 +-----
 2 files changed, 7 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 39310cf13c3a..3357b690ce90 100644
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -359,11 +359,6 @@ static int i915_pmu_event_init(struct perf_event *event)
 			if (!HAS_RC6(i915))
 				ret = -ENODEV;
 			break;
-		case I915_PMU_RC6p_RESIDENCY:
-		case I915_PMU_RC6pp_RESIDENCY:
-			if (!HAS_RC6p(i915))
-				ret = -ENODEV;
-			break;
 		default:
 			ret = -ENOENT;
 			break;
@@ -421,16 +416,12 @@ static u64 __i915_pmu_event_read(struct perf_event *event)
 						     IS_VALLEYVIEW(i915) ?
 						     VLV_GT_RENDER_RC6 :
 						     GEN6_GT_GFX_RC6);
-			intel_runtime_pm_put(i915);
-			break;
-		case I915_PMU_RC6p_RESIDENCY:
-			intel_runtime_pm_get(i915);
-			val = intel_rc6_residency_ns(i915, GEN6_GT_GFX_RC6p);
-			intel_runtime_pm_put(i915);
-			break;
-		case I915_PMU_RC6pp_RESIDENCY:
-			intel_runtime_pm_get(i915);
-			val = intel_rc6_residency_ns(i915, GEN6_GT_GFX_RC6pp);
+			if (HAS_RC6p(i915)) {
+				val += intel_rc6_residency_ns(i915,
+							      GEN6_GT_GFX_RC6p);
+				val += intel_rc6_residency_ns(i915,
+							      GEN6_GT_GFX_RC6pp);
+			}
 			intel_runtime_pm_put(i915);
 			break;
 		}
@@ -708,8 +699,6 @@ static struct attribute *i915_pmu_events_attrs[] = {
 	I915_EVENT_ATTR(interrupts, I915_PMU_INTERRUPTS),
 
 	I915_EVENT(rc6-residency,   I915_PMU_RC6_RESIDENCY,   "ns"),
-	I915_EVENT(rc6p-residency,  I915_PMU_RC6p_RESIDENCY,  "ns"),
-	I915_EVENT(rc6pp-residency, I915_PMU_RC6pp_RESIDENCY, "ns"),
 
 	NULL,
 };
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 239e8633edc9..536ee4febd74 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -137,14 +137,10 @@ enum drm_i915_pmu_engine_sample {
 
 #define I915_PMU_ACTUAL_FREQUENCY	__I915_PMU_OTHER(0)
 #define I915_PMU_REQUESTED_FREQUENCY	__I915_PMU_OTHER(1)
-
 #define I915_PMU_INTERRUPTS		__I915_PMU_OTHER(2)
-
 #define I915_PMU_RC6_RESIDENCY		__I915_PMU_OTHER(3)
-#define I915_PMU_RC6p_RESIDENCY		__I915_PMU_OTHER(4)
-#define I915_PMU_RC6pp_RESIDENCY	__I915_PMU_OTHER(5)
 
-#define I915_PMU_LAST I915_PMU_RC6pp_RESIDENCY
+#define I915_PMU_LAST I915_PMU_RC6_RESIDENCY
 
 /* Each region is a minimum of 16k, and there are at most 255 of them.
  */
-- 
2.14.1