[Intel-gfx] [PATCH] drm/i915: Restore GT performance in headless mode with DMC loaded

[Imre Deak]

On Wed, Nov 29, 2017 at 11:10:58AM +0000, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2017-11-29 10:59:27)
> > From: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
> > 
> > It seems that the DMC likes to transition between the DC states a lot when
> > there are no connected displays (no active power domains) during command
> > submission.
> > 
> > This activity on DC states has a negative impact on the performance of the
> > chip with huge latencies observed in the interrupt handlers and elsewhere.
> > Simple tests like igt/gem_latency -n 0 are slowed down by a factor of
> > eight.
> > 
> > Work around it by introducing a new power domain named,
> > POWER_DOMAIN_GT_IRQ, associtated with the "DC off" power well, which is
> > held for the duration of command submission activity.
> > 
> > v2:
> >  * Add commit text as comment in i915_gem_mark_busy. (Chris Wilson)
> >  * Protect macro body with braces. (Jani Nikula)
> > 
> > v3:
> >  * Add dedicated power domain for clarity. (Chris, Imre)
> >  * Commit message and comment text updates.
> >  * Apply to all big-core GEN9 parts apart for Skylake which is pending DMC
> >    firmware release.
> > 
> > Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100572
> > Testcase: igt/gem_exec_nop/headless
> > Cc: Imre Deak <imre.deak at intel.com>
> > Acked-by: Chris Wilson <chris at chris-wilson.co.uk>
> > Cc: Chris Wilson <chris at chris-wilson.co.uk>
> > Cc: Dmitry Rogozhkin <dmitry.v.rogozhkin at intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_drv.h         |  5 +++++
> >  drivers/gpu/drm/i915/i915_gem.c         |  4 ++++
> >  drivers/gpu/drm/i915/i915_gem_request.c | 14 ++++++++++++++
> >  drivers/gpu/drm/i915/intel_runtime_pm.c |  4 ++++
> >  4 files changed, 27 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index bddd65839f60..17340aadc566 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -398,6 +398,7 @@ enum intel_display_power_domain {
> >         POWER_DOMAIN_AUX_D,
> >         POWER_DOMAIN_GMBUS,
> >         POWER_DOMAIN_MODESET,
> > +       POWER_DOMAIN_GT_IRQ,
> >         POWER_DOMAIN_INIT,
> >  
> >         POWER_DOMAIN_NUM,
> > @@ -3285,6 +3286,10 @@ intel_info(const struct drm_i915_private *dev_priv)
> >  #define GT_FREQUENCY_MULTIPLIER 50
> >  #define GEN9_FREQ_SCALER 3
> >  
> > +#define NEEDS_CSR_GT_PERF_WA(dev_priv) \
> > +       (HAS_CSR(dev_priv) && (dev_priv)->csr.dmc_payload && \
> 
> We can't have a dmc_payload unless CSR, right?
> 
> > +       IS_GEN9_BC(dev_priv) && !IS_SKYLAKE(dev_priv))
> > +
> >  #include "i915_trace.h"
> >  
> >  static inline bool intel_vtd_active(void)
> > diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> > index 354b0546a191..feec2a621120 100644
> > --- a/drivers/gpu/drm/i915/i915_gem.c
> > +++ b/drivers/gpu/drm/i915/i915_gem.c
> > @@ -3381,7 +3381,11 @@ i915_gem_idle_work_handler(struct work_struct *work)
> >  
> >         if (INTEL_GEN(dev_priv) >= 6)
> >                 gen6_rps_idle(dev_priv);
> > +
> >         intel_runtime_pm_put(dev_priv);
> > +
> > +       if (NEEDS_CSR_GT_PERF_WA(dev_priv))
> > +               intel_display_power_put(dev_priv, POWER_DOMAIN_GT_IRQ);
> 
> Which is the outer wakeref? I expect runtime, being device-global, to be
> the outer wakeref, with display_power_put being the inner subset.

Yes, logically the runtime ref is the outer one. But
intel_display_power_get() takes a runtime ref too and both runtime and
display power references can be held for "a long time" and so can be
taken in both order.

> -Chris