[Intel-gfx] [PATCH v1] drm/i915: Enhanced for initialize partially filled pagetables

Joonas Lahtinen joonas.lahtinen at linux.intel.com
Mon Oct 2 09:03:25 UTC 2017


+ Zhenyu and Zhi

On Sat, 2017-09-30 at 02:58 +0000, Zhang, Xiaolin wrote:
> On 09/28/2017 10:25 PM, Joonas Lahtinen wrote:
> > On Thu, 2017-09-28 at 10:09 +0800, Xiaolin Zhang wrote:
> > > if vgpu active, the page table entry should be initialized after
> > > allocation and then the hypersivor can ping pages succesuffly,
> > > otherwise hypervisor will ping pages failed and the host will
> > > print
> > > a lot of annoying errors such as “ERROR gvt: guest page write
> > > error -22,
> > > gfn 0x7ada8, pa 0x7ada89a8, var 0x6, len 1” when create linux
> > > guest.
> > > 
> > > Signed-off-by: Xiaolin Zhang <xiaolin.zhang at intel.com>
> > 
> > Why does the hypervisor try to access the entries prior to them
> > being
> > made valid for hardware?
> > 
> > Regards, Joonas
> 
> Hi Joonas,
> thanks your comment. 
> I think what you ask is the point we got the error message in gvt since the current gvt
> implementation is that page under write protection and trapped should be valid 
> with correct shadow page setup and p2m translation.

My question is that if the hardware doesn't care about them being
uninitialized at this point, how can GVT? If the GVT implementation
relies heavily on how the i915 driver currently happens to behave, not
on what contracts it has with the hardware, these breakages are bound
to happen repeatedly. The code is being transformed and optimized on
daily basis, how it currently behaves is not a solid foundation for
implementing the host side virtualization.

> Actually, to work with 
> “initialize partially filled pagetables" , there is a certain refine work to do in gvt side
> (maybe less or maybe large). but before refine work done, this patch is trying to bring back 
> gvt behavior as before “initialize partially filled pagetables"patch. 

We should first minimize and then keep the vgpu specific checks to
minimum. So this would need to be fixed on the GVT side of code.

Regards, Joonas
-- 
Joonas Lahtinen
Open Source Technology Center
Intel Corporation


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