[Intel-gfx] [PATCH v2 2/2] drm/i915: enable to read CSB and CSB write pointer from HWSP in GVT-g VM

[Chris Wilson]

Quoting Joonas Lahtinen (2017-10-02 11:03:30)
> On Sat, 2017-09-30 at 13:57 +0800, Weinan Li wrote:
> > Let GVT-g VM read the CSB and CSB write pointer from virtual HWSP, not all
> > the host support this feature, need to check the BIT(3) of caps in PVINFO.
> > 
> > Signed-off-by: Weinan Li <weinan.z.li at intel.com>
> > Cc: Chris Wilson <chris at chris-wilson.co.uk>
> 
> <SNIP>
> 
> > @@ -396,6 +393,12 @@ static bool csb_force_mmio(struct drm_i915_private *i915)
> >       if (intel_vtd_active())
> >               return true;
> >  
> > +     /* GVT emulation depends upon host kernel implementation, check
> > +      * support capbility by reading PV INFO before access HWSP.
> > +      */
> 
> The comment can be dropped completely, the code is self-descriptive.
> 
> > +++ b/drivers/gpu/drm/i915/intel_lrc.c
> > @@ -722,7 +722,12 @@ static void intel_lrc_irq_handler(unsigned long data)
> >                       &engine->status_page.page_addr[I915_HWS_CSB_BUF0_INDEX];
> >               unsigned int head, tail;
> >  
> > -             /* However GVT emulation depends upon intercepting CSB mmio */
> > +             /* However GVT-g emulation depends upon host kernel
> > +              * implementation, need to check support capbility by reading PV
> > +              * INFO before access HWSP. Beside from this, another special
> > +              * configuration may also need to force use mmio, like IOMMU
> > +              * enabled.
> > +              */
> 
> s/capbility/capability/ and please rephrase this to be a kerneldoc for
> csb_use_mmio at the declaration.

This is not a description of how to use the function or even on how
csb_use_mmio work, this is why we want certain logic paths. Just a regular
old comment.
-Chris