[Intel-gfx] [PATCH 1/2] drm/i915: Move MMCD_MISC_CTRL from context w/a to standard

[Oscar Mateo]

On 10/04/2017 05:55 AM, Mika Kuoppala wrote:
> Chris Wilson <chris at chris-wilson.co.uk> writes:
>
>> Looking at gem_workarounds shows us that MMCD_MISC_CTRL is not restored
>> following a suspend-resume cycle. This implies that MMCD_MISC_CTRL is
>> not stored in the context, but is an ordinary register w/a that we need to
>> restore during init_hw.
>>
>> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
>> Cc: Mika Kuoppala <mika.kuoppala at linux.intel.com>
>> Cc: Oscar Mateo <oscar.mateo at intel.com>
> Reviewed-by: Mika Kuoppala <mika.kuoppala at linux.intel.com>

Reviewed-by: Oscar Mateo <oscar.mateo at intel.com>

I missed this one!

>> ---
>>   drivers/gpu/drm/i915/intel_engine_cs.c | 6 +++++-
>>   1 file changed, 5 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
>> index a28e2a864cf1..06044f1f48c8 100644
>> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
>> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
>> @@ -980,7 +980,11 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
>>   				  GEN9_PBE_COMPRESSED_HASH_SELECTION);
>>   		WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
>>   				  GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR);
>> -		WA_SET_BIT(MMCD_MISC_CTRL, MMCD_PCLA | MMCD_HOTSPOT_EN);
>> +
>> +		I915_WRITE(MMCD_MISC_CTRL,
>> +			   I915_READ(MMCD_MISC_CTRL) |
>> +			   MMCD_PCLA |
>> +			   MMCD_HOTSPOT_EN);
>>   	}
>>   
>>   	/* WaClearFlowControlGpgpuContextSave:skl,bxt,kbl,glk,cfl */
>> -- 
>> 2.14.2