[Intel-gfx] [PATCH 1/2] drm/i915/cnl: Fix PLL mapping.

[Ausmus, James]

On Tue, Oct 3, 2017 at 3:08 PM, Rodrigo Vivi <rodrigo.vivi at intel.com> wrote:
> On PLL Enable sequence we need to "Configure DPCLKA_CFGCR0 to turn on
> the clock for the DDI and map the DPLL to the DDI"
>
> So we first do the map and then we unset DDI_CLK_OFF to turn the clock
> on. We do this in 2 separated steps.
>
> However, on this second step where we should only unset the off bit we are
> also unmapping the ddi from the pll. So we end up using the pll 0
> for almost everything. Consequently breaking cases with more than one
> display.
>
> Fixes: 555e38d27317 ("drm/i915/cnl: DDI - PLL mapping")
> Cc: Paulo Zanoni <paulo.r.zanoni at intel.com>
> Cc: Manasi Navare <manasi.d.navare at intel.com>
> Cc: Kahola, Mika <mika.kahola at intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi at intel.com>

Reviewed-by: James Ausmus <james.ausmus at intel.com>

> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 3 +--
>  1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 55c43b333d3c..bf8ec0bd349f 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2144,8 +2144,7 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder,
>                  * register writes.
>                  */
>                 val = I915_READ(DPCLKA_CFGCR0);
> -               val &= ~(DPCLKA_CFGCR0_DDI_CLK_OFF(port) |
> -                        DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port));
> +               val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
>                 I915_WRITE(DPCLKA_CFGCR0, val);
>         } else if (IS_GEN9_BC(dev_priv)) {
>                 /* DDI -> PLL mapping  */
> --
> 2.13.5
>
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-- 


James Ausmus