[Intel-gfx] [[CI igt]] lib: Ask the kernel to quiesce the GPU

Chris Wilson chris at chris-wilson.co.uk
Thu Oct 5 17:18:34 UTC 2017


Since the introduction of debugfs/i915_drop_caches, we have offered the
ability to wait upon all outstanding batches. This is more efficient and
less error prone (one example is the use of context priorities, we have
to idle at the lowest in order not to jump over any low priority tasks
we want to wait upon) than trying to do it all in userspace. Though we
could if we wanted to, it's just easier to use the existing facility
designed for the purpose -- that we were already partially using!

Note that debugfs/i915_drop_caches has only existed since v4.2.

Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
Reviewed-by: Joonas Lahtinen <joonas.lahtinen at linux.intel.com>
Reviewed-by: Petri Latvala <petri.latvala at intel.com>
---
 lib/drmtest.c | 28 +---------------------------
 1 file changed, 1 insertion(+), 27 deletions(-)

diff --git a/lib/drmtest.c b/lib/drmtest.c
index 8a07152c..4ae023d7 100644
--- a/lib/drmtest.c
+++ b/lib/drmtest.c
@@ -159,35 +159,9 @@ static bool has_known_intel_chipset(int fd)
  */
 void gem_quiescent_gpu(int fd)
 {
-	uint32_t bbe = MI_BATCH_BUFFER_END;
-	struct drm_i915_gem_execbuffer2 execbuf;
-	struct drm_i915_gem_exec_object2 obj;
-	unsigned ring;
-
 	igt_terminate_spin_batches();
 
-	memset(&obj, 0, sizeof(obj));
-	obj.handle = gem_create(fd, 4096);
-	gem_write(fd, obj.handle, 0, &bbe, sizeof(&bbe));
-
-	memset(&execbuf, 0, sizeof(execbuf));
-	execbuf.buffers_ptr = to_user_pointer(&obj);
-	execbuf.buffer_count = 1;
-
-	for (ring = 0; ring < 1<<6; ring++) {
-		execbuf.flags = ring;
-		__gem_execbuf(fd, &execbuf);
-	}
-
-	if (gem_has_bsd2(fd)) {
-		execbuf.flags = I915_EXEC_BSD | (2 << 13);
-		__gem_execbuf(fd, &execbuf);
-	}
-
-	gem_sync(fd, obj.handle);
-	gem_close(fd, obj.handle);
-
-	igt_drop_caches_set(fd, DROP_RETIRE | DROP_FREED);
+	igt_drop_caches_set(fd, DROP_ACTIVE | DROP_RETIRE | DROP_FREED);
 }
 
 /**
-- 
2.14.2



More information about the Intel-gfx mailing list