[Intel-gfx] [PATCH 01/10] drm/i915: Separate RPS and RC6 handling for gen6+
Chris Wilson
chris at chris-wilson.co.uk
Thu Oct 5 17:36:10 UTC 2017
Quoting Sagar Arun Kamble (2017-10-04 15:07:16)
> This patch separates enable/disable of RC6 and RPS for gen6+
> platforms prior to VLV.
>
> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble at intel.com>
> Cc: Imre Deak <imre.deak at intel.com>
> Cc: Chris Wilson <chris at chris-wilson.co.uk>
> Cc: Joonas Lahtinen <joonas.lahtinen at linux.intel.com>
> Reviewed-by: Radoslaw Szwichtenberg <radoslaw.szwichtenberg at intel.com>
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 17 +++++++-------
> drivers/gpu/drm/i915/intel_pm.c | 44 +++++++++++++++++++++++++------------
> 2 files changed, 38 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index b4a6ac6..abb8524 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1136,6 +1136,13 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
> pm_iir = I915_READ(GEN8_GT_IIR(2));
> pm_mask = I915_READ(GEN6_PMINTRMSK);
> }
> + seq_printf(m, "Video Turbo Mode: %s\n",
> + yesno(rpmodectl & GEN6_RP_MEDIA_TURBO));
> + seq_printf(m, "HW control enabled: %s\n",
> + yesno(rpmodectl & GEN6_RP_ENABLE));
> + seq_printf(m, "SW control enabled: %s\n",
> + yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) ==
> + GEN6_RP_MEDIA_SW_MODE));
> seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
> pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
> seq_printf(m, "pm_intrmsk_mbz: 0x%08x\n",
> @@ -1479,7 +1486,7 @@ static int vlv_drpc_info(struct seq_file *m)
> static int gen6_drpc_info(struct seq_file *m)
> {
> struct drm_i915_private *dev_priv = node_to_i915(m->private);
> - u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
> + u32 gt_core_status, rcctl1, rc6vids = 0;
> u32 gen9_powergate_enable = 0, gen9_powergate_status = 0;
> unsigned forcewake_count;
> int count = 0;
> @@ -1498,7 +1505,6 @@ static int gen6_drpc_info(struct seq_file *m)
> gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS);
> trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
>
> - rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
> rcctl1 = I915_READ(GEN6_RC_CONTROL);
> if (INTEL_GEN(dev_priv) >= 9) {
> gen9_powergate_enable = I915_READ(GEN9_PG_ENABLE);
> @@ -1509,13 +1515,6 @@ static int gen6_drpc_info(struct seq_file *m)
> sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
> mutex_unlock(&dev_priv->rps.hw_lock);
>
> - seq_printf(m, "Video Turbo Mode: %s\n",
> - yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
> - seq_printf(m, "HW control enabled: %s\n",
> - yesno(rpmodectl1 & GEN6_RP_ENABLE));
> - seq_printf(m, "SW control enabled: %s\n",
> - yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
> - GEN6_RP_MEDIA_SW_MODE));
> seq_printf(m, "RC1e Enabled: %s\n",
> yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
> seq_printf(m, "RC6 Enabled: %s\n",
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index c66af09..fa916e0 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -6326,9 +6326,13 @@ static void gen9_disable_rps(struct drm_i915_private *dev_priv)
> I915_WRITE(GEN6_RP_CONTROL, 0);
> }
>
> -static void gen6_disable_rps(struct drm_i915_private *dev_priv)
> +static void gen6_disable_rc6(struct drm_i915_private *dev_priv)
> {
> I915_WRITE(GEN6_RC_CONTROL, 0);
> +}
> +
> +static void gen6_disable_rps(struct drm_i915_private *dev_priv)
> +{
> I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
> I915_WRITE(GEN6_RP_CONTROL, 0);
> }
> @@ -6686,7 +6690,7 @@ static void gen8_enable_rps(struct drm_i915_private *dev_priv)
> intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> }
>
> -static void gen6_enable_rps(struct drm_i915_private *dev_priv)
> +static void gen6_enable_rc6(struct drm_i915_private *dev_priv)
> {
> struct intel_engine_cs *engine;
> enum intel_engine_id id;
> @@ -6697,12 +6701,6 @@ static void gen6_enable_rps(struct drm_i915_private *dev_priv)
>
> WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
>
> - /* Here begins a magic sequence of register writes to enable
> - * auto-downclocking.
> - *
> - * Perhaps there might be some value in exposing these to
> - * userspace...
> - */
> I915_WRITE(GEN6_RC_STATE, 0);
>
> /* Clear the DBG now so we don't confuse earlier errors */
> @@ -6756,12 +6754,6 @@ static void gen6_enable_rps(struct drm_i915_private *dev_priv)
> GEN6_RC_CTL_EI_MODE(1) |
> GEN6_RC_CTL_HW_ENABLE);
>
> - /* Power down if completely idle for over 50ms */
> - I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
> - I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
> -
> - reset_rps(dev_priv, gen6_set_rps);
> -
> rc6vids = 0;
> ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
> if (IS_GEN6(dev_priv) && ret) {
> @@ -6779,6 +6771,28 @@ static void gen6_enable_rps(struct drm_i915_private *dev_priv)
> intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> }
>
> +
> +static void gen6_enable_rps(struct drm_i915_private *dev_priv)
> +{
> + WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
> +
> + /* Here begins a magic sequence of register writes to enable
> + * auto-downclocking.
> + *
> + * Perhaps there might be some value in exposing these to
> + * userspace...
> + */
> + intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
> +
> + /* Power down if completely idle for over 50ms */
> + I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
> + I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
> +
> + reset_rps(dev_priv, gen6_set_rps);
> +
> + intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
> +}
I was surprised it was so little, but the split looks correct.
Reviewed-by: Chris Wilson <chris at chris-wilson.co.uk>
-Chris
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