[Intel-gfx] [PATCH 02/10] drm/i915: Separate RPS and RC6 handling for BDW

[Chris Wilson]

Quoting Sagar Arun Kamble (2017-10-04 15:07:17)
> This patch separates RC6 and RPS enabling for BDW.
> RC6/RPS Disabling are handled through gen6 functions.
> PM Programming guide recommends a sequence within forcewakes to
> configure RC6, RPS and ring frequencies in sequence. With this
> patch the order is still maintained.
> 
> v2: Update sequence numbers in RC6 programming and comment about
> intent of reset_rps during gen8_enable_rps. (Radoslaw)
> 
> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble at intel.com>
> Cc: Imre Deak <imre.deak at intel.com>
> Cc: Chris Wilson <chris at chris-wilson.co.uk>
> Cc: Joonas Lahtinen <joonas.lahtinen at linux.intel.com>
> Reviewed-by: Radoslaw Szwichtenberg <radoslaw.szwichtenberg at intel.com>
> ---
> @@ -6645,16 +6645,18 @@ static void gen8_enable_rps(struct drm_i915_private *dev_priv)
>         if (intel_enable_rc6() & INTEL_RC6_ENABLE)
>                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
>         intel_print_rc6_info(dev_priv, rc6_mask);
> -       if (IS_BROADWELL(dev_priv))
> -               I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
> -                               GEN7_RC_CTL_TO_MODE |
> -                               rc6_mask);
> -       else
> -               I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
> -                               GEN6_RC_CTL_EI_MODE(1) |
> -                               rc6_mask);
> +       I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
> +                       GEN7_RC_CTL_TO_MODE |
> +                       rc6_mask);

Ah, presumably you noted that this function is only called for bdw.
Please make this a separate patch, and fixup the earlier IS_BROADWELL as
well.

The rest of the patch makes sense,
Reviewed-by: Chris Wilson <chris at chris-wilson.co.uk>
-Chris