[Intel-gfx] [PATCH v2 09/11] drm/i915: Create generic function to setup LLC ring frequency table

[Chris Wilson]

Quoting Sagar Arun Kamble (2017-10-06 13:13:38)
> Prepared intel_update_ring_freq function to setup ring frequency
> for applicable platforms determined by macro HAS_LLC.
> 
> v2: Replaced NEEDS_RING_FREQ_UPDATE with HAS_LLC macro. (Chris)
>     Added check while calling from intel_enable_gt_powersave.
> 
> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble at intel.com>
> Cc: Imre Deak <imre.deak at intel.com>
> Cc: Chris Wilson <chris at chris-wilson.co.uk>
> Cc: Joonas Lahtinen <joonas.lahtinen at linux.intel.com>
> Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenberg at intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 12 ++++++++----
>  1 file changed, 8 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index f7c1d5e..ce2dc5b 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -7871,6 +7871,11 @@ static void intel_init_emon(struct drm_i915_private *dev_priv)
>         dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
>  }
>  
> +static inline void intel_update_ring_freq(struct drm_i915_private *i915)
> +{
> +       gen6_update_ring_freq(i915);
> +}
> +
>  void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
>  {
>         struct intel_rps *rps = &dev_priv->pm.rps;
> @@ -8017,21 +8022,20 @@ void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
>         } else if (INTEL_GEN(dev_priv) >= 9) {
>                 gen9_enable_rc6(dev_priv);
>                 gen9_enable_rps(dev_priv);
> -               if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv))
> -                       gen6_update_ring_freq(dev_priv);
>         } else if (IS_BROADWELL(dev_priv)) {
>                 gen8_enable_rc6(dev_priv);
>                 gen8_enable_rps(dev_priv);
> -               gen6_update_ring_freq(dev_priv);
>         } else if (INTEL_GEN(dev_priv) >= 6) {
>                 gen6_enable_rc6(dev_priv);
>                 gen6_enable_rps(dev_priv);
> -               gen6_update_ring_freq(dev_priv);
>         } else if (IS_IRONLAKE_M(dev_priv)) {
>                 ironlake_enable_drps(dev_priv);
>                 intel_init_emon(dev_priv);
>         }
>  
> +       if (HAS_LLC(dev_priv))
> +               intel_update_ring_freq(dev_priv);

Hmm, actually makes sense at a hw architectural level. Some doubts as to
whether it will hold forever, but that's a problem for tomorrow.

Reviewed-by: Chris Wilson <chris at chris-wilson.co.uk>
-Chris