[Intel-gfx] [PATCH 09/14] drm/i915: Set scaler mode for NV12

[Mahesh Kumar]

Hi,


On Tuesday 10 October 2017 05:47 PM, Vidya Srinivas wrote:
> From: Chandra Konduru <chandra.konduru at intel.com>
>
> This patch sets appropriate scaler mode for NV12 format.
> In this mode, skylake scaler does either chroma-upsampling or
> chroma-upsampling and resolution scaling
>
> v2: Review comments from Ville addressed
> 	NV12 case to be checked first for setting
> 	the scaler
>
> v3: Rebased (me)
>
> v4: Rebased (me)
>
> v5: Missed the Tested-by/Reviewed-by in the previous series
> 	Adding the same to commit message in this version.
>
> v6: Rebased (me)
>
> v7: Rebased (me)
>
> v8: Rebased (me)
> 	Restricting the NV12 change for scaler to BXT and KBL
> 	in this series.
>
> Tested-by: Clinton Taylor <clinton.a.taylor at intel.com>
> Reviewed-by: Clinton Taylor <clinton.a.taylor at intel.com>
> Signed-off-by: Chandra Konduru <chandra.konduru at intel.com>
> Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti at intel.com>
> Signed-off-by: Vidya Srinivas <vidya.srinivas at intel.com>
> ---
>   drivers/gpu/drm/i915/i915_reg.h     | 1 +
>   drivers/gpu/drm/i915/intel_atomic.c | 8 +++++++-
>   2 files changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 50e65c9..976b501 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6607,6 +6607,7 @@ enum {
>   #define PS_SCALER_MODE_MASK (3 << 28)
>   #define PS_SCALER_MODE_DYN  (0 << 28)
>   #define PS_SCALER_MODE_HQ  (1 << 28)
> +#define PS_SCALER_MODE_NV12 (2 << 28)
>   #define PS_PLANE_SEL_MASK  (7 << 25)
>   #define PS_PLANE_SEL(plane) (((plane) + 1) << 25)
>   #define PS_FILTER_MASK         (3 << 23)
> diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c
> index 36d4e63..606b5e3 100644
> --- a/drivers/gpu/drm/i915/intel_atomic.c
> +++ b/drivers/gpu/drm/i915/intel_atomic.c
> @@ -325,7 +325,13 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
>   		}
>   
>   		/* set scaler mode */
> -		if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
> +		if ((IS_BROXTON(dev_priv) || IS_KABYLAKE(dev_priv)) &&
> +			plane_state && plane_state->base.fb &&
> +			plane_state->base.fb->format->format ==
> +			DRM_FORMAT_NV12) {
> +			scaler_state->scalers[*scaler_id].mode =
> +				PS_SCALER_MODE_NV12;
> +		} else if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
>   			scaler_state->scalers[*scaler_id].mode = 0;
IN CNL for NV12 (planar formats) bit 29 of PS_CTRL register should be 
set to 1b. This require respective change in 
skylake_update_primary_plane & skl_update_plane as well.
please take care of that.
better like plane_ctl calculate ps_ctl in advance only & write during 
plane_update.

-Mahesh
>   		} else if (num_scalers_need == 1 && intel_crtc->pipe != PIPE_C) {
>   			/*