[Intel-gfx] [CI] drm/i915: Use a cached mapping for the physical HWS

[Chris Wilson]

Quoting Chris Wilson (2017-10-11 12:21:06)
> Older gen use a physical address for the hardware status page, for which
> we use cache-coherent writes. As the writes are into the cpu cache, we use
> a normal WB mapped page to read the HWS, used for our seqno tracking.
> 
> Anecdotally, I observed lost breadcrumbs writes into the HWS on i965gm,
> which so far have not reoccurred with this patch. How reliable that
> evidence is remains to be seen.
> 
> v2: Explicitly pass the expected physical address to the hw
> v3: Also remember the wild writes we once had for HWS above 4G.
> 
> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> Cc: Daniel Vetter <daniel at ffwll.ch>
> Cc: Joonas Lahtinen <joonas.lahtinen at linux.intel.com>

Oops, dropped the grumpy r-b from Daniel.

I was just wanting to see if this helped gdg, but I just remembered CI
doesn't include gdg in BAT.

Tomi, still an issue as it's reasonably stable now?
-Chris