[Intel-gfx] [PATCH v5] drm/i915: enable to read CSB and CSB write pointer from HWSP in GVT-g VM

[Chris Wilson]

Quoting Weinan Li (2017-10-13 02:46:16)
> Let GVT-g VM read the CSB and CSB write pointer from virtual HWSP, not all
> the host support this feature, need to check the BIT(3) of caps in PVINFO.
> 
> v3 : Remove unnecessary comments.
> v4 : Separate VM enable patch with GVT-g implementation patch due to code
> dependency.
> v5 : Use inline for GVT virtual HWSP caps check function.
> 
> Signed-off-by: Weinan Li <weinan.z.li at intel.com>
> Cc: Chris Wilson <chris at chris-wilson.co.uk>
> Cc: Joonas Lahtinen <joonas.lahtinen at linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_pvinfo.h     | 1 +
>  drivers/gpu/drm/i915/i915_vgpu.h       | 6 ++++++
>  drivers/gpu/drm/i915/intel_engine_cs.c | 8 ++++----
>  drivers/gpu/drm/i915/intel_lrc.c       | 1 -
>  4 files changed, 11 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_pvinfo.h b/drivers/gpu/drm/i915/i915_pvinfo.h
> index 0679a58..195203f 100644
> --- a/drivers/gpu/drm/i915/i915_pvinfo.h
> +++ b/drivers/gpu/drm/i915/i915_pvinfo.h
> @@ -53,6 +53,7 @@ enum vgt_g2v_type {
>   * VGT capabilities type
>   */
>  #define VGT_CAPS_FULL_48BIT_PPGTT      BIT(2)
> +#define VGT_CAPS_HWSP_EMULATION                BIT(3)
>  
>  struct vgt_if {
>         u64 magic;              /* VGT_MAGIC */
> diff --git a/drivers/gpu/drm/i915/i915_vgpu.h b/drivers/gpu/drm/i915/i915_vgpu.h
> index b72bd29..bb83384 100644
> --- a/drivers/gpu/drm/i915/i915_vgpu.h
> +++ b/drivers/gpu/drm/i915/i915_vgpu.h
> @@ -30,6 +30,12 @@
>  
>  bool intel_vgpu_has_full_48bit_ppgtt(struct drm_i915_private *dev_priv);
>  
> +static inline bool
> +intel_vgpu_has_hwsp_emulation(struct drm_i915_private *dev_priv)
> +{
> +       return dev_priv->vgpu.caps & VGT_CAPS_HWSP_EMULATION;
> +}
> +
>  int intel_vgt_balloon(struct drm_i915_private *dev_priv);
>  void intel_vgt_deballoon(struct drm_i915_private *dev_priv);
>  
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index a59b2a3..457ebe0 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -25,6 +25,7 @@
>  #include <drm/drm_print.h>
>  
>  #include "i915_drv.h"
> +#include "i915_vgpu.h"
>  #include "intel_ringbuffer.h"
>  #include "intel_lrc.h"
>  
> @@ -386,10 +387,6 @@ static void intel_engine_init_timeline(struct intel_engine_cs *engine)
>  
>  static bool csb_force_mmio(struct drm_i915_private *i915)
>  {
> -       /* GVT emulation depends upon intercepting CSB mmio */
> -       if (intel_vgpu_active(i915))
> -               return true;
> -
>         /*
>          * IOMMU adds unpredictable latency causing the CSB write (from the
>          * GPU into the HWSP) to only be visible some time after the interrupt
> @@ -398,6 +395,9 @@ static bool csb_force_mmio(struct drm_i915_private *i915)
>         if (intel_vtd_active())
>                 return true;
>  

The comment is still interesting:
/* Older GVT emulation depends upon intercepting CSB mmio */
as it explains why we need the mmio path ere.

With that,
Reviewed-by: Chris Wilson <chris at chris-wilson.co.uk>
-Chris