[Intel-gfx] [PATCH] drm/i915/cnl: WaRsUseTimeoutMode

[Rodrigo Vivi]

On Mon, Oct 16, 2017 at 12:07:23PM +0000, David Weinehall wrote:
> On Tue, Aug 22, 2017 at 04:58:28PM -0700, Rodrigo Vivi wrote:
> > Apparently RC6 residency is lower than expected
> > with EI mode for most of the cases on CNL A0, B0 and C0.
> > 
> > This Wa doesn't solve our lower residency, but I
> > believe it is better to have it since EI is not
> > expected to work by HW engineers anyways.
> > 
> > Cc: David Weinehall <david.weinehall at linux.intel.com>
> > Cc: Mika Kuoppala <mika.kuoppala at linux.intel.com>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi at intel.com>
> 
> Sorry, I totally missed out on this one earlier. Looks correct,
> and I've tested the patch on our CNL-Y without noticing any
> regressions.
> 
> Reviewed-by: David Weinehall <david.weinehall at linux.intel.com>

merged to dinq. Thanks.

> 
> > ---
> >  drivers/gpu/drm/i915/i915_drv.h |  1 +
> >  drivers/gpu/drm/i915/intel_pm.c | 11 +++++++++--
> >  2 files changed, 10 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 7587ef53026b..cb017b7d8ccb 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -2967,6 +2967,7 @@ intel_info(const struct drm_i915_private *dev_priv)
> >  
> >  #define CNL_REVID_A0		0x0
> >  #define CNL_REVID_B0		0x1
> > +#define CNL_REVID_C0		0x2
> >  
> >  #define IS_CNL_REVID(p, since, until) \
> >  	(IS_CANNONLAKE(p) && IS_REVID(p, since, until))
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index d5ff0b9f999f..8c6d74d94799 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -6456,7 +6456,7 @@ static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
> >  {
> >  	struct intel_engine_cs *engine;
> >  	enum intel_engine_id id;
> > -	uint32_t rc6_mask = 0;
> > +	u32 rc6_mode, rc6_mask = 0;
> >  
> >  	/* 1a: Software RC state - RC0 */
> >  	I915_WRITE(GEN6_RC_STATE, 0);
> > @@ -6494,8 +6494,15 @@ static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
> >  		rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
> >  	DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE));
> >  	I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
> > +
> > +	/* WaRsUseTimeoutMode:cnl (pre-prod) */
> > +	if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_C0))
> > +		rc6_mode = GEN7_RC_CTL_TO_MODE;
> > +	else
> > +		rc6_mode = GEN6_RC_CTL_EI_MODE(1);
> > +
> >  	I915_WRITE(GEN6_RC_CONTROL,
> > -		   GEN6_RC_CTL_HW_ENABLE | GEN6_RC_CTL_EI_MODE(1) | rc6_mask);
> > +		   GEN6_RC_CTL_HW_ENABLE | rc6_mode | rc6_mask);
> >  
> >  	/*
> >  	 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
> > -- 
> > 2.13.2
> >