[Intel-gfx] [PATCH] drm/i915/cnl: DDIA Lane capability bit not set in clone mode

[Ville Syrjälä]

On Tue, Oct 17, 2017 at 03:10:16PM +0300, Ville Syrjälä wrote:
> On Mon, Oct 16, 2017 at 04:44:49PM -0700, Rodrigo Vivi wrote:
> > From: Clint Taylor <clinton.a.taylor at intel.com>
> > 
> > DDIA Lane capability control 4 lane bit is not being set by firmware during
> > clone mode boot. This occurs when multiple monitors are connected during
> > boot. The driver will configure the port for 2 lane maximum width if this
> > bit is not set.
> > 
> > Cc: Mika Kahola <mika.kahola at intel.com>
> > Signed-off-by: Clint Taylor <clinton.a.taylor at intel.com>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi at intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_ddi.c | 5 +++--
> >  1 file changed, 3 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> > index a9c0c16e3838..0ad915d71132 100644
> > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > @@ -2791,9 +2791,10 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
> >  	 * configuration so that we use the proper lane count for our
> >  	 * calculations.
> >  	 */
> > -	if (IS_GEN9_LP(dev_priv) && port == PORT_A) {
> > +	if ((IS_GEN9_LP(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
> > +	    port == PORT_A) {
> >  		if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) {
> > -			DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n");
> > +			DRM_DEBUG_KMS("BIOS forgot to set DDI_A_4_LANES for port A\n");
> >  			intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
> >  			max_lanes = 4;
> >  		}
> 
> CNL has DDI E so this doesn't make sense. If there are CNLs out there
> that don't actually use DDI E but forget to configure the bifurcation
> coreectly, then we'll need a fancier way to detect that. Ie. we need to
> be sure DDI E isn't going to be used before we can force DDI A to use
> 4 lanes.

Oh, we'd really need some way to make sure all four lanes from DDI A are
really connected to the panel. Otherwise link training would surely
fail if we try to use four lanes.

-- 
Ville Syrjälä
Intel OTC