[Intel-gfx] [PATCH] drm/i915/cnl: Remove unnecessary check in cnl_setup_private_ppat

[Daniele Ceraolo Spurio]

On 27/10/17 15:32, Michel Thierry wrote:
> There is no need check if PPGTT is disabled because that not possible
> in CNL. Execlists and GuC submission modes rely on at least aliasing
> PPGTT and even intel_sanitize_enable_ppgtt says: "We don't allow disabling
> PPGTT for gen9+ as it's a requirement for execlists, the sole mechanism
> available to submit work."
> 
> Suggested-by: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi at intel.com>
> Signed-off-by: Michel Thierry <michel.thierry at intel.com>
> ---

Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com>

>   drivers/gpu/drm/i915/i915_gem_gtt.c | 6 ------
>   1 file changed, 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 7ebfc8ee479e..302ffe0cf3c7 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -3206,12 +3206,6 @@ static void cnl_setup_private_ppat(struct intel_ppat *ppat)
>   	ppat->match = bdw_private_pat_match;
>   	ppat->clear_value = GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3);
>   
> -	/* XXX: spec is unclear if this is still needed for CNL+ */
> -	if (!USES_PPGTT(ppat->i915)) {
> -		__alloc_ppat_entry(ppat, 0, GEN8_PPAT_UC);
> -		return;
> -	}
> -
>   	__alloc_ppat_entry(ppat, 0, GEN8_PPAT_WB | GEN8_PPAT_LLC);
>   	__alloc_ppat_entry(ppat, 1, GEN8_PPAT_WC | GEN8_PPAT_LLCELLC);
>   	__alloc_ppat_entry(ppat, 2, GEN8_PPAT_WT | GEN8_PPAT_LLCELLC);
>