[Intel-gfx] [PATCH 1/4] drm/i915: Fix the missing PPAT cache attributes on CNL

[Wang, Zhi A]

Thanks for merging the patch and test. :)

-----Original Message-----
From: Rodrigo Vivi [mailto:rodrigo.vivi at gmail.com] 
Sent: Saturday, September 2, 2017 3:01 AM
To: Wang, Zhi A <zhi.a.wang at intel.com>
Cc: intel-gfx <intel-gfx at lists.freedesktop.org>; intel-gvt-dev at lists.freedesktop.org; Vivi, Rodrigo <rodrigo.vivi at intel.com>; Widawsky, Benjamin <benjamin.widawsky at intel.com>
Subject: Re: [Intel-gfx] [PATCH 1/4] drm/i915: Fix the missing PPAT cache attributes on CNL

On Thu, Aug 31, 2017 at 12:36 PM, Zhi Wang <zhi.a.wang at intel.com> wrote:
> Add back the GEN8_PPAT_WB cache attributes in 
> cnl_setup_private_ppat(), which are missed on CNL.
>
> Fixes: e34935 ("drm/i915/cnl: Setup PAT Index")

missing some numbers....

Fixes: 4e34935fcf69 ("drm/i915/cnl: Setup PAT Index.")


> Cc: Ben Widawsky <benjamin.widawsky at intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi at intel.com>
> Cc: Chris Wilson <chris at chris-wilson.co.uk>
> Suggested-by: Joonas Lahtinen <joonas.lahtinen at linux.intel.com>
> Signed-off-by: Zhi Wang <zhi.a.wang at intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi at intel.com>

I also tested here on my CNL so I'm going to merge here this first patch.
Thanks a lot.

> ---
>  drivers/gpu/drm/i915/i915_gem_gtt.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
> b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 708b95c..f18b1ec 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -2828,10 +2828,10 @@ static void cnl_setup_private_ppat(struct drm_i915_private *dev_priv)
>         I915_WRITE(GEN10_PAT_INDEX(1), GEN8_PPAT_WC | GEN8_PPAT_LLCELLC);
>         I915_WRITE(GEN10_PAT_INDEX(2), GEN8_PPAT_WT | GEN8_PPAT_LLCELLC);
>         I915_WRITE(GEN10_PAT_INDEX(3), GEN8_PPAT_UC);
> -       I915_WRITE(GEN10_PAT_INDEX(4), GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0));
> -       I915_WRITE(GEN10_PAT_INDEX(5), GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1));
> -       I915_WRITE(GEN10_PAT_INDEX(6), GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2));
> -       I915_WRITE(GEN10_PAT_INDEX(7), GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
> +       I915_WRITE(GEN10_PAT_INDEX(4), GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(0));
> +       I915_WRITE(GEN10_PAT_INDEX(5), GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(1));
> +       I915_WRITE(GEN10_PAT_INDEX(6), GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2));
> +       I915_WRITE(GEN10_PAT_INDEX(7), GEN8_PPAT_WB | 
> + GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
>  }
>
>  /* The GGTT and PPGTT need a private PPAT setup in order to handle 
> cacheability
> --
> 2.7.4
>
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--
Rodrigo Vivi
Blog: http://blog.vivi.eng.br