[Intel-gfx] [PATCH] drm/i915/cnp: Wa 1181: Fix Backlight issue

[Rodrigo Vivi]

On Tue, Sep 5, 2017 at 11:42 AM, Pandiyan, Dhinakaran
<dhinakaran.pandiyan at intel.com> wrote:
> On Wed, 2017-08-30 at 21:52 -0700, Rodrigo Vivi wrote:
>> From: "Vivi, Rodrigo" <rodrigo.vivi at intel.com>
>>
>> This workaround fixes a CNL PCH bug when changing
>> backlight from a lower frequency to a higher frequency.
>>
>> During random reboot cycles, display backlight seems to
>> be off/ dim for 2-3 mins.
>>
>> The only functional change on this patch is to
>> set bit 13 of 0xC2020 for CNL PCH.
>>
>> The rest of patch is organizing identation around
>> those bits definitions and re-organizing CFL workarounds.
>>
>> v2: Only add the bit that matters without touching others
>>     around (Jani).
>>     Rebase on top of clock gating functions rename.
>>
>
> Checked against Bspec, patch looks correct.
> Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan at intel.com>

merged to dinq. thanks for reviews and suggestions.

>
>> Cc: Jani Nikula <jani.nikula at intel.com>
>> Cc: Arthur J Runyan <arthur.j.runyan at intel.com>
>> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan at intel.com>
>> Signed-off-by: Rodrigo Vivi <rodrigo.vivi at intel.com>
>> ---
>>  drivers/gpu/drm/i915/i915_reg.h |  1 +
>>  drivers/gpu/drm/i915/intel_pm.c | 27 +++++++++++++++++++++++++--
>>  2 files changed, 26 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index e2908ae34004..bb3df56e447f 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -7482,6 +7482,7 @@ enum {
>>  #define  PCH_DPLUNIT_CLOCK_GATE_DISABLE (1<<30)
>>  #define  PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
>>  #define  PCH_CPUNIT_CLOCK_GATE_DISABLE (1<<14)
>> +#define  CNP_PWM_CGE_GATING_DISABLE (1<<13)
>>  #define  PCH_LP_PARTITION_LEVEL_DISABLE  (1<<12)
>>
>>  /* CPU: FDI_TX */
>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>> index 4bdf1fb1df7e..3473b327519d 100644
>> --- a/drivers/gpu/drm/i915/intel_pm.c
>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>> @@ -8264,8 +8264,19 @@ static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
>>       I915_WRITE(GEN7_MISCCPCTL, misccpctl);
>>  }
>>
>> +static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)
>> +{
>> +     if (!HAS_PCH_CNP(dev_priv))
>> +             return;
>> +
>> +     /* Wa #1181 */
>> +     I915_WRITE(SOUTH_DSPCLK_GATE_D, CNP_PWM_CGE_GATING_DISABLE);
>> +}
>> +
>>  static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
>>  {
>> +     cnp_init_clock_gating(dev_priv);
>> +
>>       /* This is not an Wa. Enable for better image quality */
>>       I915_WRITE(_3D_CHICKEN3,
>>                  _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
>> @@ -8285,6 +8296,16 @@ static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
>>                          SARBUNIT_CLKGATE_DIS);
>>  }
>>
>> +static void cfl_init_clock_gating(struct drm_i915_private *dev_priv)
>> +{
>> +     cnp_init_clock_gating(dev_priv);
>> +     gen9_init_clock_gating(dev_priv);
>> +
>> +     /* WaFbcNukeOnHostModify:cfl */
>> +     I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
>> +                ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
>> +}
>> +
>>  static void kbl_init_clock_gating(struct drm_i915_private *dev_priv)
>>  {
>>       gen9_init_clock_gating(dev_priv);
>> @@ -8299,7 +8320,7 @@ static void kbl_init_clock_gating(struct drm_i915_private *dev_priv)
>>               I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
>>                          GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
>>
>> -     /* WaFbcNukeOnHostModify:kbl,cfl */
>> +     /* WaFbcNukeOnHostModify:kbl */
>>       I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
>>                  ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
>>  }
>> @@ -8767,9 +8788,11 @@ void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
>>  {
>>       if (IS_CANNONLAKE(dev_priv))
>>               dev_priv->display.init_clock_gating = cnl_init_clock_gating;
>> +     else if (IS_COFFEELAKE(dev_priv))
>> +             dev_priv->display.init_clock_gating = cfl_init_clock_gating;
>>       else if (IS_SKYLAKE(dev_priv))
>>               dev_priv->display.init_clock_gating = skl_init_clock_gating;
>> -     else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
>> +     else if (IS_KABYLAKE(dev_priv))
>>               dev_priv->display.init_clock_gating = kbl_init_clock_gating;
>>       else if (IS_BROXTON(dev_priv))
>>               dev_priv->display.init_clock_gating = bxt_init_clock_gating;
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-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br