[Intel-gfx] [PATCH] drm/i915/cnl: WA FtrEnableFastAnisoL1BankingFix

[Oscar Mateo]

On 08/29/2017 04:07 PM, Rodrigo Vivi wrote:
> WA to enable HW L1 Banking fix that allows aniso to operate
> at full sample rate.
>
> Cc: Mika Kuoppala <mika.kuoppala at intel.com>
> Cc: Oscar Mateo <oscar.mateo at intel.com>
> Cc: Ben Widawsky <ben at bwidawsk.net>
> Cc: Anuj Phogat <anuj.phogat at intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi at intel.com>
> ---
>   drivers/gpu/drm/i915/i915_reg.h        | 1 +
>   drivers/gpu/drm/i915/intel_engine_cs.c | 3 +++
>   2 files changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index e2908ae34004..1ad22a824921 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8072,6 +8072,7 @@ enum {
>   #define   HSW_SAMPLE_C_PERFORMANCE	(1<<9)
>   #define   GEN8_CENTROID_PIXEL_OPT_DIS	(1<<8)
>   #define   GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC	(1<<5)
> +#define   CNL_FAST_ANISO_L1_BANKING_FIX	(1<<4)

Why CNL_ instead of GEN10_ prefix? (out of curiosity)

>   #define   GEN8_SAMPLER_POWER_BYPASS_DIS	(1<<1)
>   
>   #define GEN9_HALF_SLICE_CHICKEN7	_MMIO(0xe194)
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index a6ac9d0a4156..4b9b7828802d 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -1090,6 +1090,9 @@ static int cnl_init_workarounds(struct intel_engine_cs *engine)
>   	/* WaPushConstantDereferenceHoldDisable:cnl */
>   	WA_SET_BIT(GEN7_ROW_CHICKEN2, PUSH_CONSTANT_DEREF_DISABLE);
>   
> +	/* FtrEnableFastAnisoL1BankingFix: cnl */
> +	WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3, CNL_FAST_ANISO_L1_BANKING_FIX);
> +

I have this only for B0 onwards, but I guess you glossed over this 
because you know more than me about which CNL stepping is the production 
one, so:
Rviewed-by: Oscar Mateo <oscar.mateo at intel.com>

>   	/* WaEnablePreemptionGranularityControlByUMD:cnl */
>   	ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1);
>   	if (ret)