[Intel-gfx] [PATCH] drm/i915: Re-enable per-engine reset for Broxton

[Michel Thierry]

On 05/09/17 06:57, Chris Wilson wrote:
> Quoting Chris Wilson (2017-08-21 15:55:34)
>> Quoting Michel Thierry (2017-08-18 18:23:42)
>>> The corruption in CSB mmio reads we were seeing has been tracked down to
>>> incorrectly touching forcewake of all domains, following an engine reset.
>>> It is still a mistery why we only catched this in Broxton, since it
>>> could happen in any platform.
>>>
>>> With that fix already merged, commit 4055dc75d6b5 ("drm/i915: Stop
>>> touching forcewake following a gen6+ engine reset"), lets try to enable
>>> per-engine resets in Broxton one more time.
>>>
>>> This reverts commit f188258bde0f ("drm/i915: Disable per-engine reset for
>>> Broxton").
>>>
>>> Cc: Chris Wilson <chris at chris-wilson.co.uk>
>>> Signed-off-by: Michel Thierry <michel.thierry at intel.com>
>>
>> My bxt has survived about 72 hours of hang testing, which is far more
>> than it was able to previously.
>>
>> Acked-by: Chris Wilson <chris at chris-wilson.co.uk>
>> Tested-by: Chris Wilson <chris at chris-wilson.co.uk>
> 
> Uh oh, seemingly just hit it again...

Was it because the CSBs were 0's?

A couple of times I saw a spurious CSB event (0x12 - preempted & 
complete), after an already 'complete' event. That was also hitting the 
assert because the ctx-id would be 'wrong'. I think we could ignore the 
0x12 event and it will continue.