[Intel-gfx] [PATCH 02/20] drm/i915/gen9+: Separate RPS and RC6 handling

[Szwichtenberg, Radoslaw]

On Fri, 2017-09-01 at 12:55 +0530, Sagar Arun Kamble wrote:
> With GuC based SLPC, frequency control will be moved to GuC and Host will
> continue to control RC6 and Ring frequency setup. SLPC can be enabled in
> the GuC setup path and can happen in parallel in GuC with other i915 setup.
> Hence we can do away with deferred RPS enabling. This needs separate
> handling of RPS, RC6 and ring frequencies in driver flows. We can still use
> the *gt_powersave routines with separate status variables of RPS, RC6 and
> SLPC. With this patch, RC6 and ring frequencies setup(if applicable) can be
> tracked through rps.rc6_enabled and RPS through rps.rps_enabled.
> Also, Active RPS check in suspend flow is needed for platforms with RC6
> and RPS enabling/disabling coupled together. RPM suspend depends only on
> RC6 though. Hence Active RPS check is done only for non-Gen9 platforms.
> 
> v2: Changing parameter to dev_priv for IS_GEN9 and HAS_RUNTIME_PM and line
>     spacing changes. (David)
>     and commit message update for checkpatch issues.
> 
> v3: Rebase.
> 
> v4: Commit message update.
> 
> v5: Updated intel_enable_gt_powersave and intel_disable_gt_powersave
>     routines with separated RPS and RC6 handling and rebase. Commit message
>     update.(Sagar)
> 
> v6: Added comments at the definition of rc6_enabled.
> 
> v7: s/rps.enabled/rps.rps_enabled. With gen9 preproduction RPS disabling
>     changes removed, updating rps_enabled in enable/disable_gt_powersave.
>     Added checks for rc6_enabled and rps_enabled for gen9+ platforms.
> 
> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble at intel.com>
Reviewed-by: Radoslaw Szwichtenberg <radoslaw.szwichtenberg at intel.com>