[Intel-gfx] [PATCH 2/2] drm/i915/cnp: Wa 1179

[Rodrigo Vivi]

"CNL PCH chance of hang when software accesses south display
registers after hotplug is enabled.
Workaround: Program 0xC2000 bits 11:8 = 0xF before enabling
south display hotplug detection."

"Workaround only needs to be applied to pre-production steppings
used in graphics capable SKUs, but it is easier to apply to
everything, and does not hurt."

Suggested-by: Ben Widawsky <ben at bwidawsk.net>
Cc: Ben Widawsky <ben at bwidawsk.net>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan at intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi at intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 2 ++
 drivers/gpu/drm/i915/intel_pm.c | 6 ++++++
 2 files changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0b03260a3967..532c9c7bdc51 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7474,6 +7474,8 @@ enum {
 #define SOUTH_CHICKEN2		_MMIO(0xc2004)
 #define  FDI_MPHY_IOSFSB_RESET_STATUS	(1<<13)
 #define  FDI_MPHY_IOSFSB_RESET_CTL	(1<<12)
+#define  CHASSIS_CLK_REQ_DURATION_MASK	(0xf<<8)
+#define  CHASSIS_CLK_REQ_DURATION(x)	((x)<<8)
 #define  LPT_PWM_GRANULARITY		(1<<5)
 #define  DPLS_EDP_PPS_FIX_DIS		(1<<0)
 
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 09ecc8e3b2d3..e49682a5ab0e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8366,12 +8366,18 @@ static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
 
 static void cnp_init_clock_gating(struct drm_i915_private *dev_priv)
 {
+	u32 val;
 	if (!HAS_PCH_CNP(dev_priv))
 		return;
 
 	/* Wa #1181 */
 	I915_WRITE(SOUTH_DSPCLK_GATE_D, I915_READ(SOUTH_DSPCLK_GATE_D) |
 		   CNP_PWM_CGE_GATING_DISABLE);
+
+	/* Wa #1179 */
+	val = I915_READ(SOUTH_CHICKEN1) & ~CHASSIS_CLK_REQ_DURATION_MASK;
+	val |= CHASSIS_CLK_REQ_DURATION(0xf);
+	I915_WRITE(SOUTH_CHICKEN1, val);
 }
 
 static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
-- 
2.13.2