[Intel-gfx] [PATCH 2/2] drm/i915: Name the IPS_PCODE_CONTROL bit

[Chris Wilson]

Quoting Ville Syrjala (2017-09-12 16:34:11)
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> 
> Give a name to the bit which tells pcode to control IPS.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h      | 1 +
>  drivers/gpu/drm/i915/intel_display.c | 3 ++-
>  2 files changed, 3 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index f9f9fcc833c5..91d5a8cbe79d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7974,6 +7974,7 @@ enum {
>  #define   GEN6_PCODE_WRITE_D_COMP              0x11
>  #define   HSW_PCODE_DE_WRITE_FREQ_REQ          0x17
>  #define   DISPLAY_IPS_CONTROL                  0x19

/* See also IPS_CTL */
?

> +#define     IPS_PCODE_CONTROL                  (1 << 30)
>  #define   HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A
>  #define   GEN9_PCODE_SAGV_CONTROL              0x21
>  #define     GEN9_SAGV_DISABLE                  0x0
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 0871807850a9..524217d6292e 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4956,7 +4956,8 @@ void hsw_enable_ips(struct intel_crtc *crtc)
>         assert_plane_enabled(dev_priv, crtc->plane);
>         if (IS_BROADWELL(dev_priv)) {
>                 mutex_lock(&dev_priv->rps.hw_lock);
> -               WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
> +               WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,
> +                                               IPS_ENABLE | IPS_PCODE_CONTROL));

Numbers match up, so
Reviewed-by: Chris Wilson <chris at chris-wilson.co.uk>
-Chris