[Intel-gfx] [PATCH 1/3] drm/i915: Trim gen8_irq_handler

[Pandiyan, Dhinakaran]

On Thu, 2017-09-14 at 09:37 +0100, Chris Wilson wrote:
> Quoting Pandiyan, Dhinakaran (2017-09-14 08:20:21)
> > 
> > On Wed, 2017-09-13 at 19:18 +0100, Chris Wilson wrote:
> > > The goal here is to trim an excess posting read and keep the predicates
> > 
> > Curious why we do the posting reads, is that a hardware requirement?
> 
> In most cases, no. In very few cases, we do need a delay in order to be
> sure the hw has processed the write before we continue (e.g. when
> enabling interrupts). But really it all started as a bad idea to try and
> move the regs over to WC with manual flushing, and cargo-culted since
> then.

That explains the writes followed by a read in this file! Thanks for the
interesting piece of background.

>  The challenge is that now those delays are in place, removing them
> requires care.
> -Chris
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