[Intel-gfx] [PATCH] drm/i915: Don't rmw PIPESTAT enable bits

[Chris Wilson]

Quoting Ville Syrjala (2017-09-14 16:17:31)
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> 
> i830 seems to occasionally forget the PIPESTAT enable bits when
> we read the register. These aren't the only registers on i830 that
> have problems with RMW, as reading the double buffered plane
> registers returns the latched value rather than the last written
> value. So something similar is perhaps going on with PIPESTAT.
> 
> This corruption results on vblank interrupts occasionally turning off
> on their own, which leads to vblank timeouts and generally a stuck
> display subsystem.
> 
> So let's not RMW the pipestat enable bits, and instead use the cached
> copy we have around.
> 
> Cc: Imre Deak <imre.deak at intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>

Well it didn't make my 845g any worse. Still has

[  245.683349] [drm:pipe_config_err] *ERROR* mismatch in base.adjusted_mode.flags (2) (expected 0, found 2)
[  245.683382] [drm:pipe_config_err] *ERROR* mismatch in base.adjusted_mode.flags (8) (expected 0, found 8)
[  245.683427] pipe state doesn't match!

if you are interested.

How occasional and which test in particular hits the issue?
-Chris