[Intel-gfx] [PATCH 00/31] Add support for GuC-based SLPC
Sagar Arun Kamble
sagar.a.kamble at intel.com
Tue Sep 19 17:41:36 UTC 2017
SLPC (Single Loop Power Controller) is a replacement for some host-based
power management features. The SLPC implementation runs in GuC firmware.
This series has been tested with SKL/APL/KBL GuC firmware v9 and v10
which are yet to be released on 01.org.
The graphics power management features in SLPC are called GTPERF,
BALANCER, and DCC.
1. GTPERF is a combination of DFPS (Dynamic FPS) and Turbo. DFPS adjusts
requested graphics frequency to maintain target framerate. Turbo adjusts
requested graphics frequency to maintain target GT busyness.
2. BALANCER adjusts balance between power budgets for IA and GT in power
limited scenarios.
3. DCC (Duty Cycle Control) adjusts requested graphics frequency and stalls
guc-scheduler to maintain actual graphics frequency in efficient range.
This series activates GTPERF Turbo and BALANCER in GuC SLPC.
Patch to enable SLPC by default on platforms having support is removed
from this series as there are following new changes to be added in future
before we enable GuC/SLPC by default:
1. Link waitboost with SLPC.
2. Handle CPG as part of SLPC.
3. IA p-state logic update with GuC submission.
In order to enable CI/PnP testing of SLPC and to avoid frequent
rebase, this series should be safe for merge with feature in disabled
state.
v2: Addressed review comments on v1. Removed patch to enable SLPC by
default.
v3: Addressed WARNING in igt at drv_module_reload_basic flagged by trybot BAT.
Added change for sanitizing GT PM during reset. Added separate patch
for sysfs interface to know HW requested frequency. Also, earlier
patches did not go as series hence were not correctly picked up by BAT.
v4: Changes to multiple patches. CI BAT is passing. Performance run on SKL
GT2 done and shows perf at parity with Host Turbo. For BXT, SLPC
improves performance when GuC is enabled compared to Host Turbo.
This series keeps only support of 9.18 firmware for better readability.
If needed, other SLPC interfaces for different GuC version will be
added later.
v5: This series incorporates feedback from code reviews on earlier series
and adds following new changes:
1. More changes for separation of RPS and RC6 handling for Gen9.
2. Tied up SLPC enabling with GuC load/GuC submission sequence.
3. SLPC structures are defined explicitly for event input/output.
4. Definition of SLPC parameter control and task control functions
agnostic to the underlying param definitions as they might
change with GuC versions and prepared helpers for common tasks.
5. Transition of i915 overrides done through host to guc events
to shared data and single reset event.
6. Handling SLPC status post reset through shared memory.
7. Derived helpers for setting frequency limits.
8. Removed sysfs interface to know RPNSWREQ as it is available in
debugfs interface i915_frequency_info.
9. Simple igt test to verify SLPC configuration by i915 in various
driver scenarios is prepared.
v6: This series adds following new changes:
1. Updated intel_guc_send for SLPC to receive output data from GuC.
2. Added task overrides and min frequency overrides in intel_slpc_init.
min frequency is set to Rpe.
3. New debugfs interface added to set/unset/read SLPC parameters
other than tasks and frequencies. SLPC reset post parameter update
added.
4. SLPC parameters persist as part of i915-GuC shared data hence not
overriding frequency limits while re-enabling SLPC.
5. Other minor fixes to clear pm_rps_events, clflush the shared data.
v7: This series adds following new changes:
1. Reordered patches. SLPC communication interfaces (structures and
functions) are pulled into patches earlier in the series.
2. Eliminated dependency on i915.enable_slpc at various functions where
rps_enabled is available.
3. s/i915_ggtt_offset/guc_ggtt_offset and sanitization of parameter
in intel_uc_sanitize_options.
v8: Activated Balancer. Changed prototype of SLPC functions to accept
struct intel_slpc as parameter instead of drm_i915_private.
v9: Separated RPS, RC6 and Ring frequency configuration for gen6+.
Added TDR specific handling of SLPC reset. Some more improvements for
support of function pointers for rps busy, idle, boost functions.
This series is based on GuC code restructuring and fixes series at
https://patchwork.freedesktop.org/series/30351/.
VIZ-6889, VIZ-6890
Cc: Chris Wilson <chris at chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vetter at intel.com>
Cc: Beuchat, Marc <marc.beuchat at intel.com>
Cc: Radoslaw Szwichtenberg <radoslaw.szwichtenberg at intel.com>
Cc: Jeff McGee <jeff.mcgee at intel.com>
Cc: Arkadiusz Hiler <arkadiusz.hiler at intel.com>
Cc: Oscar Mateo <oscar.mateo at intel.com>
Cc: Michał Winiarski <michal.winiarski at intel.com>
Tested-by: Radoslaw Szwichtenberg <radoslaw.szwichtenberg at intel.com>
Sagar Arun Kamble (22):
drm/i915/debugfs: Create generic string tokenize function and update
CRC control parsing
drm/i915: Separate RPS and RC6 handling for gen6+
drm/i915: Separate RPS and RC6 handling for BDW
drm/i915: Separate RPS and RC6 handling for VLV
drm/i915: Separate RPS and RC6 handling for CHV
drm/i915: Name i915_runtime_pm structure in dev_priv as "rpm"
drm/i915: Name structure in dev_priv that contains RPS/RC6 state as
"pm"
drm/i915: Rename intel_enable_rc6 to intel_rc6_enabled
drm/i915: Create generic function to setup ring frequency table
drm/i915: Create generic functions to control RC6, RPS
drm/i915: Introduce separate status variable for RC6 and Ring
frequency setup
drm/i915: Define RPS idle, busy, boost function pointers
drm/i915/slpc: Lay out SLPC init/enable/disable/cleanup helpers
drm/i915/slpc: Add SLPC communication interfaces
drm/i915/slpc: Allocate/Release/Initialize SLPC shared data
drm/i915/slpc: Add parameter set/unset/get, task control/status
functions
drm/i915/slpc: Send RESET event to enable SLPC during Load/TDR
drm/i915/slpc: Add support for min/max frequency control
drm/i915/slpc: Add debugfs support to read/write/revert the parameters
drm/i915/slpc: Add SLPC banner to RPS debugfs interfaces.
drm/i915/slpc: Add Kabylake SLPC support
drm/i915/slpc: Add Geminilake SLPC support
Tom O'Rourke (9):
drm/i915/slpc: Add has_slpc capability flag
drm/i915/slpc: Add enable_slpc module parameter
drm/i915/slpc: Sanitize GuC version
drm/i915/slpc: Enable SLPC in GuC if supported
drm/i915/slpc: Send SHUTDOWN event
drm/i915/slpc: Add enable/disable controls for SLPC tasks
drm/i915/slpc: Add i915_slpc_info to debugfs
drm/i915/slpc: Add SKL SLPC Support
drm/i915/slpc: Add Broxton SLPC support
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/i915_debugfs.c | 383 ++++++++---
drivers/gpu/drm/i915/i915_drv.c | 12 +-
drivers/gpu/drm/i915/i915_drv.h | 44 +-
drivers/gpu/drm/i915/i915_gem.c | 6 +-
drivers/gpu/drm/i915/i915_gem_request.c | 4 +-
drivers/gpu/drm/i915/i915_gpu_error.c | 4 +-
drivers/gpu/drm/i915/i915_guc_submission.c | 8 +-
drivers/gpu/drm/i915/i915_irq.c | 101 +--
drivers/gpu/drm/i915/i915_params.c | 5 +
drivers/gpu/drm/i915/i915_params.h | 1 +
drivers/gpu/drm/i915/i915_pci.c | 4 +
drivers/gpu/drm/i915/i915_sysfs.c | 104 +--
drivers/gpu/drm/i915/intel_cdclk.c | 40 +-
drivers/gpu/drm/i915/intel_csr.c | 15 +-
drivers/gpu/drm/i915/intel_display.c | 14 +-
drivers/gpu/drm/i915/intel_drv.h | 15 +-
drivers/gpu/drm/i915/intel_guc.c | 27 +-
drivers/gpu/drm/i915/intel_guc.h | 6 +
drivers/gpu/drm/i915/intel_guc_loader.c | 18 +
drivers/gpu/drm/i915/intel_pipe_crc.c | 88 +--
drivers/gpu/drm/i915/intel_pm.c | 673 +++++++++++-------
drivers/gpu/drm/i915/intel_runtime_pm.c | 26 +-
drivers/gpu/drm/i915/intel_sideband.c | 6 +-
drivers/gpu/drm/i915/intel_slpc.c | 1028 ++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_slpc.h | 286 ++++++++
drivers/gpu/drm/i915/intel_uc.c | 37 +
drivers/gpu/drm/i915/intel_uc_common.h | 2 +
28 files changed, 2419 insertions(+), 539 deletions(-)
create mode 100644 drivers/gpu/drm/i915/intel_slpc.c
create mode 100644 drivers/gpu/drm/i915/intel_slpc.h
--
1.9.1
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