[Intel-gfx] [PATCH 23/31] drm/i915/slpc: Add support for min/max frequency control
Sagar Arun Kamble
sagar.a.kamble at intel.com
Tue Sep 19 17:41:59 UTC 2017
Update sysfs and debugfs functions to set SLPC
parameters when setting max/min frequency.
v1: Update for SLPC 2015.2.4 (params for both slice and unslice)
Replace HAS_SLPC with intel_slpc_active() (Paulo)
v2-v4: Rebase.
v5: Removed typecasting the frequency values to u32. (Chris)
Changed intel_slpc_active to guc.slpc.enabled. Carved out
SLPC helpers to set min and max frequencies.
v6: Rebase. Doing explicit SLPC reset on setting frequency to start sane
and covered with RPM get/put. Caching SLPC limits post enabling first.
v7: Rebase due to change in the dev_priv->pm.rps structure.
Signed-off-by: Tom O'Rourke <Tom.O'Rourke at intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble at intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 48 ++++++++++++++++++++++++++++---
drivers/gpu/drm/i915/i915_sysfs.c | 36 ++++++++++++++++++++----
drivers/gpu/drm/i915/intel_slpc.c | 56 +++++++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_slpc.h | 5 ++++
4 files changed, 135 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 9356a69..dbfe185 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4381,7 +4381,13 @@ static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
if (INTEL_GEN(dev_priv) < 6)
return -ENODEV;
- *val = intel_gpu_freq(dev_priv, dev_priv->pm.rps.max_freq_softlimit);
+ if (intel_slpc_active(&dev_priv->guc.slpc))
+ *val = intel_gpu_freq(dev_priv,
+ dev_priv->guc.slpc.max_unslice_freq);
+ else
+ *val = intel_gpu_freq(dev_priv,
+ dev_priv->pm.rps.max_freq_softlimit);
+
return 0;
}
@@ -4398,20 +4404,32 @@ static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
+ intel_runtime_pm_get(dev_priv);
+
ret = mutex_lock_interruptible(&dev_priv->pm.pcu_lock);
- if (ret)
+ if (ret) {
+ intel_runtime_pm_put(dev_priv);
return ret;
+ }
/*
* Turbo will still be enabled, but won't go above the set value.
*/
val = intel_freq_opcode(dev_priv, val);
+ if (intel_slpc_active(&dev_priv->guc.slpc)) {
+ ret = intel_slpc_max_freq_set(&dev_priv->guc.slpc, val);
+ mutex_unlock(&dev_priv->pm.pcu_lock);
+ intel_runtime_pm_put(dev_priv);
+ return ret;
+ }
+
hw_max = rps->max_freq;
hw_min = rps->min_freq;
if (val < hw_min || val > hw_max || val < rps->min_freq_softlimit) {
mutex_unlock(&dev_priv->pm.pcu_lock);
+ intel_runtime_pm_put(dev_priv);
return -EINVAL;
}
@@ -4422,6 +4440,8 @@ static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
mutex_unlock(&dev_priv->pm.pcu_lock);
+ intel_runtime_pm_put(dev_priv);
+
return 0;
}
@@ -4437,7 +4457,13 @@ static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
if (INTEL_GEN(dev_priv) < 6)
return -ENODEV;
- *val = intel_gpu_freq(dev_priv, dev_priv->pm.rps.min_freq_softlimit);
+ if (intel_slpc_active(&dev_priv->guc.slpc))
+ *val = intel_gpu_freq(dev_priv,
+ dev_priv->guc.slpc.min_unslice_freq);
+ else
+ *val = intel_gpu_freq(dev_priv,
+ dev_priv->pm.rps.min_freq_softlimit);
+
return 0;
}
@@ -4453,21 +4479,33 @@ static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
+ intel_runtime_pm_get(dev_priv);
+
ret = mutex_lock_interruptible(&dev_priv->pm.pcu_lock);
- if (ret)
+ if (ret) {
+ intel_runtime_pm_put(dev_priv);
return ret;
+ }
/*
* Turbo will still be enabled, but won't go below the set value.
*/
val = intel_freq_opcode(dev_priv, val);
+ if (intel_slpc_active(&dev_priv->guc.slpc)) {
+ ret = intel_slpc_min_freq_set(&dev_priv->guc.slpc, val);
+ mutex_unlock(&dev_priv->pm.pcu_lock);
+ intel_runtime_pm_put(dev_priv);
+ return ret;
+ }
+
hw_max = dev_priv->pm.rps.max_freq;
hw_min = dev_priv->pm.rps.min_freq;
if (val < hw_min ||
val > hw_max || val > dev_priv->pm.rps.max_freq_softlimit) {
mutex_unlock(&dev_priv->pm.pcu_lock);
+ intel_runtime_pm_put(dev_priv);
return -EINVAL;
}
@@ -4478,6 +4516,8 @@ static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
mutex_unlock(&dev_priv->pm.pcu_lock);
+ intel_runtime_pm_put(dev_priv);
+
return 0;
}
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index 8add849..a2470f0 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -325,9 +325,14 @@ static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct device_attribute
{
struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
- return snprintf(buf, PAGE_SIZE, "%d\n",
- intel_gpu_freq(dev_priv,
- dev_priv->pm.rps.max_freq_softlimit));
+ if (intel_slpc_active(&dev_priv->guc.slpc))
+ return snprintf(buf, PAGE_SIZE, "%d\n",
+ intel_gpu_freq(dev_priv,
+ dev_priv->guc.slpc.max_unslice_freq));
+ else
+ return snprintf(buf, PAGE_SIZE, "%d\n",
+ intel_gpu_freq(dev_priv,
+ dev_priv->pm.rps.max_freq_softlimit));
}
static ssize_t gt_max_freq_mhz_store(struct device *kdev,
@@ -348,6 +353,13 @@ static ssize_t gt_max_freq_mhz_store(struct device *kdev,
val = intel_freq_opcode(dev_priv, val);
+ if (intel_slpc_active(&dev_priv->guc.slpc)) {
+ ret = intel_slpc_max_freq_set(&dev_priv->guc.slpc, val);
+ mutex_unlock(&dev_priv->pm.pcu_lock);
+ intel_runtime_pm_put(dev_priv);
+ return ret ? ret : count;
+ }
+
if (val < dev_priv->pm.rps.min_freq ||
val > dev_priv->pm.rps.max_freq ||
val < dev_priv->pm.rps.min_freq_softlimit) {
@@ -382,9 +394,14 @@ static ssize_t gt_min_freq_mhz_show(struct device *kdev, struct device_attribute
{
struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
- return snprintf(buf, PAGE_SIZE, "%d\n",
- intel_gpu_freq(dev_priv,
- dev_priv->pm.rps.min_freq_softlimit));
+ if (intel_slpc_active(&dev_priv->guc.slpc))
+ return snprintf(buf, PAGE_SIZE, "%d\n",
+ intel_gpu_freq(dev_priv,
+ dev_priv->guc.slpc.min_unslice_freq));
+ else
+ return snprintf(buf, PAGE_SIZE, "%d\n",
+ intel_gpu_freq(dev_priv,
+ dev_priv->pm.rps.min_freq_softlimit));
}
static ssize_t gt_min_freq_mhz_store(struct device *kdev,
@@ -405,6 +422,13 @@ static ssize_t gt_min_freq_mhz_store(struct device *kdev,
val = intel_freq_opcode(dev_priv, val);
+ if (intel_slpc_active(&dev_priv->guc.slpc)) {
+ ret = intel_slpc_min_freq_set(&dev_priv->guc.slpc, val);
+ mutex_unlock(&dev_priv->pm.pcu_lock);
+ intel_runtime_pm_put(dev_priv);
+ return ret ? ret : count;
+ }
+
if (val < dev_priv->pm.rps.min_freq ||
val > dev_priv->pm.rps.max_freq ||
val > dev_priv->pm.rps.max_freq_softlimit) {
diff --git a/drivers/gpu/drm/i915/intel_slpc.c b/drivers/gpu/drm/i915/intel_slpc.c
index b0a17ef..d0fd402 100644
--- a/drivers/gpu/drm/i915/intel_slpc.c
+++ b/drivers/gpu/drm/i915/intel_slpc.c
@@ -496,6 +496,10 @@ bool intel_slpc_get_status(struct intel_slpc *slpc)
switch (data.global_state) {
case SLPC_GLOBAL_STATE_RUNNING:
/* Capture required state from SLPC here */
+ slpc->max_unslice_freq = data.task_state_data.max_unslice_freq *
+ GEN9_FREQ_SCALER;
+ slpc->min_unslice_freq = data.task_state_data.min_unslice_freq *
+ GEN9_FREQ_SCALER;
ret = true;
break;
case SLPC_GLOBAL_STATE_ERROR:
@@ -536,6 +540,58 @@ static void intel_slpc_restore_default_rps(struct intel_slpc *slpc)
I915_WRITE(GEN6_RP_CONTROL, slpc->rp_control);
}
+/*
+ * TODO: Add separate interfaces to set Max/Min Slice frequency.
+ * Since currently both slice and unslice are configured to same
+ * frequencies these unified interface relying on Unslice frequencies
+ * should be sufficient. These functions take frequency opcode as input.
+ */
+int intel_slpc_max_freq_set(struct intel_slpc *slpc, u32 val)
+{
+ struct drm_i915_private *dev_priv = slpc_to_i915(slpc);
+
+ if (val < dev_priv->pm.rps.min_freq ||
+ val > dev_priv->pm.rps.max_freq ||
+ val < slpc->min_unslice_freq)
+ return -EINVAL;
+
+ intel_slpc_set_param(slpc,
+ SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ,
+ intel_gpu_freq(dev_priv, val));
+ intel_slpc_set_param(slpc,
+ SLPC_PARAM_GLOBAL_MAX_GT_SLICE_FREQ_MHZ,
+ intel_gpu_freq(dev_priv, val));
+
+ intel_slpc_enable(slpc);
+
+ slpc->max_unslice_freq = val;
+
+ return 0;
+}
+
+int intel_slpc_min_freq_set(struct intel_slpc *slpc, u32 val)
+{
+ struct drm_i915_private *dev_priv = slpc_to_i915(slpc);
+
+ if (val < dev_priv->pm.rps.min_freq ||
+ val > dev_priv->pm.rps.max_freq ||
+ val > slpc->max_unslice_freq)
+ return -EINVAL;
+
+ intel_slpc_set_param(slpc,
+ SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
+ intel_gpu_freq(dev_priv, val));
+ intel_slpc_set_param(slpc,
+ SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ,
+ intel_gpu_freq(dev_priv, val));
+
+ intel_slpc_enable(slpc);
+
+ slpc->min_unslice_freq = val;
+
+ return 0;
+}
+
void intel_slpc_init(struct intel_slpc *slpc)
{
struct intel_guc *guc = slpc_to_guc(slpc);
diff --git a/drivers/gpu/drm/i915/intel_slpc.h b/drivers/gpu/drm/i915/intel_slpc.h
index 20c342b..ae857d3 100644
--- a/drivers/gpu/drm/i915/intel_slpc.h
+++ b/drivers/gpu/drm/i915/intel_slpc.h
@@ -29,6 +29,9 @@ struct intel_slpc {
bool tdr_reset;
struct i915_vma *vma;
u32 rp_control;
+ /* i915 cached SLPC frequency limits */
+ u32 min_unslice_freq;
+ u32 max_unslice_freq;
};
static inline int intel_slpc_enabled(void)
@@ -262,6 +265,8 @@ void intel_slpc_read_shared_data(struct intel_slpc *slpc,
const char *intel_slpc_get_state_str(enum slpc_global_state state);
bool intel_slpc_get_status(struct intel_slpc *slpc);
void intel_slpc_save_default_rps(struct intel_slpc *slpc);
+int intel_slpc_max_freq_set(struct intel_slpc *slpc, u32 val);
+int intel_slpc_min_freq_set(struct intel_slpc *slpc, u32 val);
void intel_slpc_init(struct intel_slpc *slpc);
void intel_slpc_cleanup(struct intel_slpc *slpc);
void intel_slpc_enable(struct intel_slpc *slpc);
--
1.9.1
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