[Intel-gfx] [PATCH 2/2] drm/i915/cnl: Fix SSEU Device Status.

[Oscar Mateo]

On 09/18/2017 11:49 AM, Rodrigo Vivi wrote:
> CNL adds an extra register for slice/subslice information.
> Although no SKU is planed with an extra slice let's already
> handle this extra piece of information so we don't have the
> risk in future of getting a part that might have chosen this
> part of the die instead of other slices or anything like that.
>
> Also if subslice is disabled the information of eu ack for that
> is garbage, so let's skip checks for eu if subslice is disabled
> as we skip the subslice if slice is disabled.
>
> The rest is pretty much like gen9.
>
> Cc: Oscar Mateo <oscar.mateo at intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi at intel.com>
> ---
>   drivers/gpu/drm/i915/i915_debugfs.c | 52 ++++++++++++++++++++++++++++++++++++-
>   drivers/gpu/drm/i915/i915_reg.h     |  6 +++++
>   2 files changed, 57 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index ca6fa6d122c6..3bf9304baf33 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -4575,6 +4575,54 @@ static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv,
>   	}
>   }
>   
> +static void gen10_sseu_device_status(struct drm_i915_private *dev_priv,
> +				     struct sseu_dev_info *sseu)
> +{
> +	const struct intel_device_info *info = INTEL_INFO(dev_priv);
> +	int s_max = 4, ss_max = 3;
> +	int s, ss;
> +	u32 s_reg[s_max], eu_reg[2 * s_max], eu_mask[2];
> +
> +	for (s = 0; s < s_max; s++) {
> +		s_reg[s] = I915_READ(GEN10_SLICE_PGCTL_ACK(s));
> +		eu_reg[2 * s] = I915_READ(GEN10_SS01_EU_PGCTL_ACK(s));
> +		eu_reg[2 * s + 1] = I915_READ(GEN10_SS23_EU_PGCTL_ACK(s));
> +	}
> +
> +	eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
> +		     GEN9_PGCTL_SSA_EU19_ACK |
> +		     GEN9_PGCTL_SSA_EU210_ACK |
> +		     GEN9_PGCTL_SSA_EU311_ACK;
> +	eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
> +		     GEN9_PGCTL_SSB_EU19_ACK |
> +		     GEN9_PGCTL_SSB_EU210_ACK |
> +		     GEN9_PGCTL_SSB_EU311_ACK;
> +
> +	for (s = 0; s < s_max; s++) {
> +		if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
> +			/* skip disabled slice */
> +			continue;
> +
> +		sseu->slice_mask |= BIT(s);
> +		sseu->subslice_mask = info->sseu.subslice_mask;
> +
> +		for (ss = 0; ss < ss_max; ss++) {
> +			unsigned int eu_cnt;
> +
> +			if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
> +				/* skip disabled subslice */
> +				continue;
> +
> +			eu_cnt = 2 * hweight32(eu_reg[2 * s + ss / 2] &
> +					       eu_mask[ss % 2]);
> +			sseu->eu_total += eu_cnt;
> +			sseu->eu_per_subslice = max_t(unsigned int,
> +						      sseu->eu_per_subslice,
> +						      eu_cnt);
> +		}
> +	}
> +}
> +
>   static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
>   				    struct sseu_dev_info *sseu)
>   {
> @@ -4716,8 +4764,10 @@ static int i915_sseu_status(struct seq_file *m, void *unused)
>   		cherryview_sseu_device_status(dev_priv, &sseu);
>   	} else if (IS_BROADWELL(dev_priv)) {
>   		broadwell_sseu_device_status(dev_priv, &sseu);
> -	} else if (INTEL_GEN(dev_priv) >= 9) {
> +	} else if (IS_GEN9(dev_priv)) {
>   		gen9_sseu_device_status(dev_priv, &sseu);
> +	} else if (INTEL_GEN(dev_priv) >= 10) {
> +		gen10_sseu_device_status(dev_priv, &sseu);
>   	}
>   
>   	intel_runtime_pm_put(dev_priv);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 4db5deddfb9f..a8cb9c17e6df 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8018,11 +8018,17 @@ enum {
>   #define   CHV_EU311_PG_ENABLE		(1<<1)
>   
>   #define GEN9_SLICE_PGCTL_ACK(slice)	_MMIO(0x804c + (slice)*0x4)
> +#define GEN10_SLICE_PGCTL_ACK(slice)	((slice) == 3 ? _MMIO(0x8080) : \
> +					 GEN9_SLICE_PGCTL_ACK((slice)))
>   #define   GEN9_PGCTL_SLICE_ACK		(1 << 0)
>   #define   GEN9_PGCTL_SS_ACK(subslice)	(1 << (2 + (subslice)*2))
>   
>   #define GEN9_SS01_EU_PGCTL_ACK(slice)	_MMIO(0x805c + (slice)*0x8)
> +#define GEN10_SS01_EU_PGCTL_ACK(slice)	((slice) == 3 ? _MMIO(0x808c) : \
> +					 GEN9_SS01_EU_PGCTL_ACK((slice)))
>   #define GEN9_SS23_EU_PGCTL_ACK(slice)	_MMIO(0x8060 + (slice)*0x8)
> +#define GEN10_SS23_EU_PGCTL_ACK(slice)	((slice) == 3 ? _MMIO(0x8090) : \
> +					 GEN9_SS23_EU_PGCTL_ACK((slice)))
>   #define   GEN9_PGCTL_SSA_EU08_ACK	(1 << 0)
>   #define   GEN9_PGCTL_SSA_EU19_ACK	(1 << 2)
>   #define   GEN9_PGCTL_SSA_EU210_ACK	(1 << 4)

Now there is an IS_CANNONLAKE check that can be removed from 
gen9_sseu_device_status (1dd7a3e, "drm/i915/cnl: Add slice and subslice 
information to debugfs").

Apart from that:
Reviewed-by: Oscar Mateo <oscar.mateo at intel.com>