[Intel-gfx] [PATCH 2/2] drm/i915/psr: Set frames before SU entry for psr2

[Ville Syrjälä]

On Wed, Sep 20, 2017 at 08:02:35PM +0530, vathsala nagaraju wrote:
> Set frames before SU entry value for max resync frame count of
> dpcd register 2009, bit field 0:3.
> 
> Cc: Rodrigo Vivi <rodrigo.vivi at intel.com>
> CC: Puthikorn Voravootivat <puthik at chromium.org>
> Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju at intel.com>
> ---
>  drivers/gpu/drm/i915/intel_psr.c | 12 ++++++++++--
>  1 file changed, 10 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index acb5094..04b253f 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -327,6 +327,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
>  	 */
>  	uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
>  	uint32_t val;
> +	uint8_t sink_latency;
>  
>  	val = idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
>  
> @@ -334,8 +335,15 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
>  	 * mesh at all with our frontbuffer tracking. And the hw alone isn't
>  	 * good enough. */
>  	val |= EDP_PSR2_ENABLE |
> -		EDP_SU_TRACK_ENABLE |
> -		EDP_FRAMES_BEFORE_SU_ENTRY;
> +		EDP_SU_TRACK_ENABLE;
> +
> +	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_SYNCHRONIZATION_LATENCY,
> +				&sink_latency)) {

== 1

> +		sink_latency = sink_latency & DP_MAX_RESYNC_FRAME_CNT_MASK;
> +		val |= (sink_latency + 1) << EDP_PSR2_FRAME_BEFORE_SU_SHIFT;
> +	} else {
> +		val |= EDP_FRAMES_BEFORE_SU_ENTRY;
> +	}
>  
>  	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
>  		val |= EDP_PSR2_TP2_TIME_2500;
> -- 
> 1.9.1
> 
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-- 
Ville Syrjälä
Intel OTC