[Intel-gfx] [PATCH 19/21] drm/i915: disable platform support for vGPU huge gtt pages

[Zhenyu Wang]

On 2017.09.22 18:32:50 +0100, Matthew Auld wrote:
> Currently gvt gtt handling doesn't support huge page entries, so disable
> for now.
> 
> v2: remove useless 48b PPGTT check
> 
> Suggested-by: Zhenyu Wang <zhenyuw at linux.intel.com>
> Signed-off-by: Matthew Auld <matthew.auld at intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen at linux.intel.com>
> Cc: Chris Wilson <chris at chris-wilson.co.uk>
> Cc: Zhenyu Wang <zhenyuw at linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_gem.c | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 750c04002304..f98d8a08167b 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -4831,6 +4831,14 @@ int i915_gem_init(struct drm_i915_private *dev_priv)
>  
>  	mutex_lock(&dev_priv->drm.struct_mutex);
>  
> +	/* We need to fallback to 4K pages since gvt gtt handling doesn't
> +	 * support huge page entries - we will need to check either hypervisor
> +	 * mm can support huge guest page or just do emulation in gvt.
> +	 */
> +	if (intel_vgpu_active(dev_priv))
> +		mkwrite_device_info(dev_priv)->page_sizes =
> +			I915_GTT_PAGE_SIZE_4K;
> +
>  	dev_priv->mm.unordered_timeline = dma_fence_context_alloc(1);
>  
>  	if (!i915_modparams.enable_execlists) {
> -- 
> 2.13.5
> 

Reviewed-by: Zhenyu Wang <zhenyuw at linux.intel.com>

thanks
-- 
Open Source Technology Center, Intel ltd.

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