[Intel-gfx] [PATCH 2/2] drm/i915: add missing DPLL fields to i915_shared_dplls_info

[Paulo Zanoni]

Looks like we've been forgetting to add these since a long time ago.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni at intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 13fc259..2b2faa6 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3481,6 +3481,22 @@ static int i915_shared_dplls_info(struct seq_file *m, void *unused)
 		seq_printf(m, " fp0:     0x%08x\n", pll->state.hw_state.fp0);
 		seq_printf(m, " fp1:     0x%08x\n", pll->state.hw_state.fp1);
 		seq_printf(m, " wrpll:   0x%08x\n", pll->state.hw_state.wrpll);
+		seq_printf(m, " spll:    0x%08x\n", pll->state.hw_state.spll);
+		seq_printf(m, " ctrl1:   0x%08x\n", pll->state.hw_state.ctrl1);
+		seq_printf(m, " cfgcr1:  0x%08x\n", pll->state.hw_state.cfgcr1);
+		seq_printf(m, " cfgcr2:  0x%08x\n", pll->state.hw_state.cfgcr2);
+		seq_printf(m, " cfgcr0:  0x%08x\n", pll->state.hw_state.cfgcr0);
+		seq_printf(m, " ebb0:    0x%08x\n", pll->state.hw_state.ebb0);
+		seq_printf(m, " ebb4:    0x%08x\n", pll->state.hw_state.ebb4);
+		seq_printf(m, " pll0:    0x%08x\n", pll->state.hw_state.pll0);
+		seq_printf(m, " pll1:    0x%08x\n", pll->state.hw_state.pll1);
+		seq_printf(m, " pll2:    0x%08x\n", pll->state.hw_state.pll2);
+		seq_printf(m, " pll3:    0x%08x\n", pll->state.hw_state.pll3);
+		seq_printf(m, " pll6:    0x%08x\n", pll->state.hw_state.pll6);
+		seq_printf(m, " pll8:    0x%08x\n", pll->state.hw_state.pll8);
+		seq_printf(m, " pll9:    0x%08x\n", pll->state.hw_state.pll9);
+		seq_printf(m, " pll10:   0x%08x\n", pll->state.hw_state.pll10);
+		seq_printf(m, " pcsdw12: 0x%08x\n", pll->state.hw_state.pcsdw12);
 	}
 	drm_modeset_unlock_all(dev);
 
-- 
2.9.5