[Intel-gfx] [PATCH 1/2] drm/i915: add the BXT and CNL DPLL registers to pipe_config_compare

[Rodrigo Vivi]

Shouldn't we filter them out per platform?

Anyways it is good for me

Reviewed-by: Rodrigo Vivi <rodrigo.vivi at intel.com>

On Fri, Sep 22, 2017 at 08:53:42PM +0000, Paulo Zanoni wrote:
> Looks like we were missing them.
> 
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni at intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 026fa54..64a4105 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -11336,6 +11336,18 @@ intel_pipe_config_compare(struct drm_i915_private *dev_priv,
>  	PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
>  	PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
>  	PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
> +	PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
> +	PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
> +	PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
> +	PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
> +	PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
> +	PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
> +	PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
> +	PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
> +	PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
> +	PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
> +	PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
> +	PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
>  
>  	PIPE_CONF_CHECK_X(dsi_pll.ctrl);
>  	PIPE_CONF_CHECK_X(dsi_pll.div);
> -- 
> 2.9.5
> 
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