[Intel-gfx] [PATCH 11/21] drm/i915: disable GTT cache for 2M pages

[Mika Kuoppala]

Matthew Auld <matthew.auld at intel.com> writes:

> When SW enables the use of 2M/1G pages, it must disable the GTT cache.
>
> v2: don't disable for Cherryview which doesn't even support 48b PPGTT!
>
> v3: explicitly check that the system does support 2M/1G pages
>
> Signed-off-by: Matthew Auld <matthew.auld at intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen at linux.intel.com>
> Cc: Chris Wilson <chris at chris-wilson.co.uk>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 8 +++++---
>  1 file changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index c66af09e27a7..719a1c5f1ffa 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -8483,10 +8483,12 @@ static void bdw_init_clock_gating(struct drm_i915_private *dev_priv)
>  
>  	/*
>  	 * WaGttCachingOffByDefault:bdw
> -	 * GTT cache may not work with big pages, so if those
> -	 * are ever enabled GTT cache may need to be disabled.
> +	 * The GTT cache must be disabled if the system is planning to use
> +	 * 2M/1G pages.

s/is planning to/is using

Reviewed-by: Mika Kuoppala <mika.kuoppala at linux.intel.com>

>  	 */
> -	I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
> +	I915_WRITE(HSW_GTT_CACHE_EN,
> +		   HAS_PAGE_SIZES(dev_priv, I915_GTT_PAGE_SIZE_2M) ? 0 :
> +		   GTT_CACHE_EN_ALL);
>  
>  	/* WaKVMNotificationOnConfigChange:bdw */
>  	I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)
> -- 
> 2.13.5
>
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