[Intel-gfx] [PATCH 09/12] drm/i915/cnl: Only request voltage frequency switching when needed.

[Rodrigo Vivi]

At cdclk initialization at spec they tell us to always use dvfs
or avoid change cdclk if it fails.

Here on pll sequence, spec tells us to only use dvfs "if the
frequency will result in a change to the voltage requirement."

So in order to respect that and avoid necessary interactions with
PCODE we compare our current needed level with the current set level
and only perform dvfs sequences when we need to change that level.

Cc: Mika Kahola <mika.kahola at intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni at intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi at intel.com>
---
 drivers/gpu/drm/i915/intel_cdclk.c    |  9 +++++++++
 drivers/gpu/drm/i915/intel_dpll_mgr.c | 16 +++++++++-------
 drivers/gpu/drm/i915/intel_drv.h      |  1 +
 3 files changed, 19 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index af8411c2a6b9..516cd4f920b5 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -1535,6 +1535,15 @@ void cnl_dvfs_post_change(struct drm_i915_private *dev_priv, int level)
 	mutex_unlock(&dev_priv->rps.hw_lock);
 }
 
+bool cnl_dvfs_need_change(struct drm_i915_private *dev_priv, int level)
+{
+	int old_level;
+	mutex_lock(&dev_priv->rps.hw_lock);
+	sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &old_level);
+	mutex_unlock(&dev_priv->rps.hw_lock);
+	return level != old_level;
+}
+
 static void cnl_set_cdclk(struct drm_i915_private *dev_priv,
 			  const struct intel_cdclk_state *cdclk_state)
 {
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index a71a6c396bbd..ca1ea475c517 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -1980,9 +1980,10 @@ static void cnl_ddi_pll_enable(struct drm_i915_private *dev_priv,
 			       struct intel_shared_dpll *pll)
 {
 	uint32_t val;
-	int ret;
+	int ret = 0;
 	int level;
 	int cdclk, portclk;
+	bool change_level;
 
 	/* 1. Enable DPLL power in DPLL_ENABLE. */
 	val = I915_READ(CNL_DPLL_ENABLE(pll->id));
@@ -2021,7 +2022,12 @@ static void cnl_ddi_pll_enable(struct drm_i915_private *dev_priv,
 	 * requirement, follow the Display Voltage Frequency Switching
 	 * (DVFS) Sequence Before Frequency Change
 	 */
-	ret = cnl_dvfs_pre_change(dev_priv);
+	cdclk = dev_priv->cdclk.hw.cdclk;
+	portclk = intel_ddi_port_clock(dev_priv, pll->id);
+	level = cnl_get_dvfs_level(cdclk, portclk);
+	change_level = cnl_dvfs_need_change(dev_priv, level);
+	if (change_level)
+		ret = cnl_dvfs_pre_change(dev_priv);
 
 	/* 6. Enable DPLL in DPLL_ENABLE. */
 	val = I915_READ(CNL_DPLL_ENABLE(pll->id));
@@ -2041,12 +2047,8 @@ static void cnl_ddi_pll_enable(struct drm_i915_private *dev_priv,
 	 * requirement, follow the Display Voltage Frequency Switching
 	 * (DVFS) Sequence After Frequency Change
 	 */
-	if (ret == 0) {
-		cdclk = dev_priv->cdclk.hw.cdclk;
-		portclk = intel_ddi_port_clock(dev_priv, pll->id);
-		level = cnl_get_dvfs_level(cdclk, portclk);
+	if (change_level && ret == 0)
 		cnl_dvfs_post_change(dev_priv, level);
-	}
 
 	/*
 	 * 9. turn on the clock for the DDI and map the DPLL to the DDI
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 934ccf17f8ab..200061def48e 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1325,6 +1325,7 @@ void cnl_init_cdclk(struct drm_i915_private *dev_priv);
 void cnl_uninit_cdclk(struct drm_i915_private *dev_priv);
 int cnl_dvfs_pre_change(struct drm_i915_private *dev_priv);
 void cnl_dvfs_post_change(struct drm_i915_private *dev_priv, int level);
+bool cnl_dvfs_need_change(struct drm_i915_private *dev_priv, int level);
 void bxt_init_cdclk(struct drm_i915_private *dev_priv);
 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv);
-- 
2.13.5