[Intel-gfx] [PATCH v2] drm/i915: set minimum CD clock to twice the BCLK.

[Abhay Kumar]

In glk when device boots with 1366x768 panel, HDA codec doesn't comeup.
This result in no audio forever as cdclk is < 96Mhz.
This chagne will ensure CD clock to be twice of  BCLK.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102937
Signed-off-by: Abhay Kumar <abhay.kumar at intel.com>
---
 drivers/gpu/drm/i915/intel_audio.c | 34 +++++++++++++++++++++++-----------
 drivers/gpu/drm/i915/intel_cdclk.c | 21 +++++++++++++++++++++
 drivers/gpu/drm/i915/intel_drv.h   |  1 +
 3 files changed, 45 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_audio.c b/drivers/gpu/drm/i915/intel_audio.c
index 709d6ca68074..ca9859a69eb2 100644
--- a/drivers/gpu/drm/i915/intel_audio.c
+++ b/drivers/gpu/drm/i915/intel_audio.c
@@ -723,15 +723,38 @@ static void i915_audio_component_put_power(struct device *kdev)
 	intel_display_power_put(kdev_to_i915(kdev), POWER_DOMAIN_AUDIO);
 }
 
+/* Get CDCLK in kHz  */
+static int i915_audio_component_get_cdclk_freq(struct device *kdev)
+{
+        struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
+
+        if (WARN_ON_ONCE(!HAS_DDI(dev_priv)))
+                return -ENODEV;
+
+        return dev_priv->cdclk.hw.cdclk;
+}
+
 static void i915_audio_component_codec_wake_override(struct device *kdev,
 						     bool enable)
 {
 	struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
 	u32 tmp;
+	int current_cdclk, min_cdclk;
 
 	if (!IS_GEN9_BC(dev_priv))
 		return;
 
+	current_cdclk = i915_audio_component_get_cdclk_freq(kdev);
+
+	/*
+	 * Before probing for HDA Codec we need to make sure
+	 * "The CD clock frequency must be at least twice
+         * the frequency of the Azalia BCLK."
+	 */
+	if (INTEL_GEN(dev_priv) >= 9 && current_cdclk <= 192000) {
+		intel_cdclk_bump(dev_priv);
+	}
+
 	i915_audio_component_get_power(kdev);
 
 	/*
@@ -753,17 +776,6 @@ static void i915_audio_component_codec_wake_override(struct device *kdev,
 	i915_audio_component_put_power(kdev);
 }
 
-/* Get CDCLK in kHz  */
-static int i915_audio_component_get_cdclk_freq(struct device *kdev)
-{
-	struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
-
-	if (WARN_ON_ONCE(!HAS_DDI(dev_priv)))
-		return -ENODEV;
-
-	return dev_priv->cdclk.hw.cdclk;
-}
-
 /*
  * get the intel_encoder according to the parameter port and pipe
  * intel_encoder is saved by the index of pipe
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index dc7db8a2caf8..9426e1b7badc 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -1516,6 +1516,27 @@ void bxt_init_cdclk(struct drm_i915_private *dev_priv)
 }
 
 /**
+ * intel_cdclk_bump - Increase cdclk to 2* BCLK
+ * @dev_priv: i915 device
+ *
+ * Increase CDCLK for GKL and CNL. This is done only
+ * during HDA codec probe.
+ */
+void intel_cdclk_bump(struct drm_i915_private *dev_priv)
+{
+	struct intel_cdclk_state cdclk_state;
+
+	cdclk_state = dev_priv->cdclk.hw;
+
+	if (IS_GEMINILAKE(dev_priv)) {
+		cdclk_state.cdclk = glk_calc_cdclk((2*96000));
+		cdclk_state.vco = glk_de_pll_vco(dev_priv, cdclk_state.cdclk);
+		cdclk_state.voltage_level = bxt_calc_voltage_level(cdclk_state.cdclk);
+		bxt_set_cdclk(dev_priv, &cdclk_state);
+	}
+}
+
+/**
  * bxt_uninit_cdclk - Uninitialize CDCLK on BXT
  * @dev_priv: i915 device
  *
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index d1452fd2a58d..5192753df3dc 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1417,6 +1417,7 @@ void skl_uninit_cdclk(struct drm_i915_private *dev_priv);
 void cnl_init_cdclk(struct drm_i915_private *dev_priv);
 void cnl_uninit_cdclk(struct drm_i915_private *dev_priv);
 void bxt_init_cdclk(struct drm_i915_private *dev_priv);
+void intel_cdclk_bump(struct drm_i915_private *dev_priv);
 void bxt_uninit_cdclk(struct drm_i915_private *dev_priv);
 void icl_init_cdclk(struct drm_i915_private *dev_priv);
 void icl_uninit_cdclk(struct drm_i915_private *dev_priv);
-- 
2.7.4