[Intel-gfx] [PATCH 20/22] drm/i915/icl: Wa_1406838659

[Oscar Mateo]

Disable CGPSF unit clock gating to prevent an issue.

Cc: Mika Kuoppala <mika.kuoppala at linux.intel.com>
Signed-off-by: Oscar Mateo <oscar.mateo at intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 13 ++++++++-----
 drivers/gpu/drm/i915/intel_pm.c |  6 ++++++
 2 files changed, 14 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 84e5a59..af4fee2 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3823,15 +3823,18 @@ enum {
  * GEN10 clock gating regs
  */
 #define SLICE_UNIT_LEVEL_CLKGATE	_MMIO(0x94d4)
-#define  SARBUNIT_CLKGATE_DIS		(1 << 5)
-#define  RCCUNIT_CLKGATE_DIS		(1 << 7)
-#define  MSCUNIT_CLKGATE_DIS		(1 << 10)
+#define   SARBUNIT_CLKGATE_DIS		(1 << 5)
+#define   RCCUNIT_CLKGATE_DIS		(1 << 7)
+#define   MSCUNIT_CLKGATE_DIS		(1 << 10)
 
 #define SUBSLICE_UNIT_LEVEL_CLKGATE	_MMIO(0x9524)
-#define  GWUNIT_CLKGATE_DIS		(1 << 16)
+#define   GWUNIT_CLKGATE_DIS		(1 << 16)
 
 #define UNSLICE_UNIT_LEVEL_CLKGATE	_MMIO(0x9434)
-#define  VFUNIT_CLKGATE_DIS		(1 << 20)
+#define   VFUNIT_CLKGATE_DIS		(1 << 20)
+
+#define INF_UNIT_LEVEL_CLKGATE		_MMIO(0x9560)
+#define   CGPSF_CLKGATE_DIS		(1 << 3)
 
 /*
  * Display engine regs
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 9771f56..1acc719 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8575,6 +8575,12 @@ static void icl_init_clock_gating(struct drm_i915_private *dev_priv)
 	I915_WRITE(GEN10_L3_CHICKEN_MODE_REGISTER,
 		   (I915_READ(GEN10_L3_CHICKEN_MODE_REGISTER) |
 		    GEN11_I2M_WRITE_DISABLE));
+
+	/* Wa_1406838659:icl (pre-prod) */
+	if (IS_ICL_REVID(dev_priv, ICL_REVID_A0, ICL_REVID_C0))
+		I915_WRITE(INF_UNIT_LEVEL_CLKGATE,
+			   (I915_READ(INF_UNIT_LEVEL_CLKGATE) |
+			    CGPSF_CLKGATE_DIS));
 }
 
 static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
-- 
1.9.1