[Intel-gfx] [PATCH 15/18] drm/i915/execlists: Try preempt-reset from hardirq timer context
Chris Wilson
chris at chris-wilson.co.uk
Mon Apr 9 11:14:10 UTC 2018
When circumstances allow, trying resetting the engine directly from the
preemption timeout handler. As this is softirq context, we have to be
careful both not to sleep and not to spin on anything we may be
interrupting (e.g. the submission tasklet).
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala at linux.intel.com>
Cc: Michał Winiarski <michal.winiarski at intel.com>
CC: Michel Thierry <michel.thierry at intel.com>
Cc: Jeff McGee <jeff.mcgee at intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
---
drivers/gpu/drm/i915/intel_lrc.c | 35 +++++-
drivers/gpu/drm/i915/selftests/intel_lrc.c | 123 +++++++++++++++++++++
2 files changed, 157 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index ca1c54af2877..4f1e985b3cdb 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -550,6 +550,38 @@ static void inject_preempt_context(struct intel_engine_cs *engine)
execlists_set_active(execlists, EXECLISTS_ACTIVE_PREEMPT);
}
+static int try_preempt_reset(struct intel_engine_execlists *execlists)
+{
+ int err = -EBUSY;
+
+ if (tasklet_trylock(&execlists->tasklet)) {
+ struct intel_engine_cs *engine =
+ container_of(execlists, typeof(*engine), execlists);
+ const unsigned int bit = I915_RESET_ENGINE + engine->id;
+ unsigned long *lock = &engine->i915->gpu_error.flags;
+
+ execlists->tasklet.func(execlists->tasklet.data);
+
+ if (!execlists_is_active(execlists,
+ EXECLISTS_ACTIVE_PREEMPT_TIMEOUT)) {
+ /* Nothing to do; the tasklet was just delayed. */
+ err = 0;
+ } else if (!test_and_set_bit(bit, lock)) {
+ tasklet_disable_nosync(&execlists->tasklet);
+ err = i915_reset_engine(engine,
+ "preemption time out");
+ tasklet_enable(&execlists->tasklet);
+
+ clear_bit(bit, lock);
+ wake_up_bit(lock, bit);
+ }
+
+ tasklet_unlock(&execlists->tasklet);
+ }
+
+ return err;
+}
+
static enum hrtimer_restart preempt_timeout(struct hrtimer *hrtimer)
{
struct intel_engine_execlists *execlists =
@@ -571,7 +603,8 @@ static enum hrtimer_restart preempt_timeout(struct hrtimer *hrtimer)
intel_engine_dump( engine, &p, "%s\n", engine->name);
}
- queue_work(system_highpri_wq, &execlists->preempt_reset);
+ if (try_preempt_reset(execlists))
+ queue_work(system_highpri_wq, &execlists->preempt_reset);
return HRTIMER_NORESTART;
}
diff --git a/drivers/gpu/drm/i915/selftests/intel_lrc.c b/drivers/gpu/drm/i915/selftests/intel_lrc.c
index aed2502419ee..72d2770e5d71 100644
--- a/drivers/gpu/drm/i915/selftests/intel_lrc.c
+++ b/drivers/gpu/drm/i915/selftests/intel_lrc.c
@@ -555,6 +555,128 @@ static int live_preempt_timeout(void *arg)
return err;
}
+static void __softirq_begin(void)
+{
+ local_bh_disable();
+}
+
+static void __softirq_end(void)
+{
+ local_bh_enable();
+}
+
+static void __hardirq_begin(void)
+{
+ local_irq_disable();
+}
+
+static void __hardirq_end(void)
+{
+ local_irq_enable();
+}
+
+static int live_preempt_reset(void *arg)
+{
+ struct drm_i915_private *i915 = arg;
+ struct intel_engine_cs *engine;
+ struct i915_gem_context *ctx;
+ enum intel_engine_id id;
+ struct spinner spin;
+ int err = -ENOMEM;
+
+ if (!HAS_LOGICAL_RING_PREEMPTION(i915))
+ return 0;
+
+ mutex_lock(&i915->drm.struct_mutex);
+
+ if (spinner_init(&spin, i915))
+ goto err_unlock;
+
+ ctx = kernel_context(i915);
+ if (!ctx)
+ goto err_spin;
+
+ for_each_engine(engine, i915, id) {
+ static const struct {
+ const char *name;
+ void (*critical_section_begin)(void);
+ void (*critical_section_end)(void);
+ } phases[] = {
+ { "softirq", __softirq_begin, __softirq_end },
+ { "hardirq", __hardirq_begin, __hardirq_end },
+ { }
+ };
+ const typeof(*phases) *p;
+
+ for (p = phases; p->name; p++) {
+ struct i915_request *rq;
+
+ rq = spinner_create_request(&spin, ctx, engine,
+ MI_NOOP);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ goto err_ctx;
+ }
+
+ i915_request_add(rq);
+ if (!wait_for_spinner(&spin, rq)) {
+ i915_gem_set_wedged(i915);
+ err = -EIO;
+ goto err_ctx;
+ }
+
+ /* Flush to give try_preempt_reset a chance */
+ do {
+ tasklet_schedule(&engine->execlists.tasklet);
+ usleep_range(100, 1000);
+ tasklet_kill(&engine->execlists.tasklet);
+ } while (test_bit(ENGINE_IRQ_EXECLIST,
+ &engine->irq_posted));
+ GEM_BUG_ON(i915_request_completed(rq));
+
+ GEM_TRACE("%s triggering %s reset\n",
+ engine->name, p->name);
+ p->critical_section_begin();
+
+ /* Trick execution of the tasklet from within reset */
+ set_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
+ execlists_set_active(&engine->execlists,
+ EXECLISTS_ACTIVE_PREEMPT_TIMEOUT);
+
+ err = try_preempt_reset(&engine->execlists);
+
+ p->critical_section_end();
+ if (err) {
+ pr_err("Preempt softirq reset failed on %s, irq_posted? %d, tasklet state %lx\n",
+ engine->name,
+ test_bit(ENGINE_IRQ_EXECLIST,
+ &engine->irq_posted),
+ engine->execlists.tasklet.state);
+ spinner_end(&spin);
+ i915_gem_set_wedged(i915);
+ goto err_ctx;
+ }
+ GEM_BUG_ON(test_bit(ENGINE_IRQ_EXECLIST,
+ &engine->irq_posted));
+
+ if (flush_test(i915, I915_WAIT_LOCKED)) {
+ err = -EIO;
+ goto err_ctx;
+ }
+ }
+ }
+
+ err = 0;
+err_ctx:
+ kernel_context_close(ctx);
+err_spin:
+ spinner_fini(&spin);
+err_unlock:
+ flush_test(i915, I915_WAIT_LOCKED);
+ mutex_unlock(&i915->drm.struct_mutex);
+ return err;
+}
+
int intel_execlists_live_selftests(struct drm_i915_private *i915)
{
static const struct i915_subtest tests[] = {
@@ -562,6 +684,7 @@ int intel_execlists_live_selftests(struct drm_i915_private *i915)
SUBTEST(live_preempt),
SUBTEST(live_late_preempt),
SUBTEST(live_preempt_timeout),
+ SUBTEST(live_preempt_reset),
};
return i915_subtests(tests, i915);
}
--
2.17.0
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