[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/18] drm/i915/execlists: Set queue priority from secondary port

[Patchwork]

== Series Details ==

Series: series starting with [01/18] drm/i915/execlists: Set queue priority from secondary port
URL   : https://patchwork.freedesktop.org/series/41357/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
fe34e7d49f28 drm/i915/execlists: Set queue priority from secondary port
-:25: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#25: 
References: f6322eddaff7 ("drm/i915/preemption: Allow preemption between submission ports")

-:25: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit f6322eddaff7 ("drm/i915/preemption: Allow preemption between submission ports")'
#25: 
References: f6322eddaff7 ("drm/i915/preemption: Allow preemption between submission ports")

total: 1 errors, 1 warnings, 0 checks, 9 lines checked
7c05a3c646d6 drm/i915/execlists: Refactor out complete_preempt_context()
b7ecf299a4f9 drm/i915: Move engine reset prepare/finish to backends
2b9aff94cf13 drm/i915: Split execlists/guc reset preparations
69d92c7b2ef7 drm/i915/execlists: Flush pending preemption events during reset
-:69: WARNING:LONG_LINE: line over 100 characters
#69: FILE: drivers/gpu/drm/i915/intel_lrc.c:908:
+				(i915->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_BUF_LO(engine, 0)));

-:87: WARNING:LONG_LINE: line over 100 characters
#87: FILE: drivers/gpu/drm/i915/intel_lrc.c:922:
+			head = readl(i915->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine)));

-:104: WARNING:LONG_LINE: line over 100 characters
#104: FILE: drivers/gpu/drm/i915/intel_lrc.c:936:
+			  head, GEN8_CSB_READ_PTR(readl(i915->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine)))), fw ? "" : "?",

-:105: WARNING:LONG_LINE: line over 100 characters
#105: FILE: drivers/gpu/drm/i915/intel_lrc.c:937:
+			  tail, GEN8_CSB_WRITE_PTR(readl(i915->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine)))), fw ? "" : "?");

total: 0 errors, 4 warnings, 0 checks, 192 lines checked
8584674c645e drm/i915/breadcrumbs: Keep the fake irq armed across reset
5333a7b17913 drm/i915: Combine tasklet_kill and tasklet_disable
-:39: WARNING:MEMORY_BARRIER: memory barrier without comment
#39: FILE: drivers/gpu/drm/i915/intel_lrc.c:1764:
+	smp_mb();

total: 0 errors, 1 warnings, 0 checks, 26 lines checked
69c64b744f61 drm/i915: Stop parking the signaler around reset
3b598171e856 drm/i915: Be irqsafe inside reset
26a3324ce9c0 drm/i915/execlists: Make submission tasklet hardirq safe
277f79ddc081 drm/i915/guc: Make submission tasklet hardirq safe
c3667f5a4ad6 drm/i915: Allow init_breadcrumbs to be used from irq context
c9c18eae9f33 drm/i915: Compile out engine debug for release
68bac469bf86 drm/i915/execlists: Force preemption via reset on timeout
-:56: ERROR:SPACING: space prohibited after that open parenthesis '('
#56: FILE: drivers/gpu/drm/i915/intel_lrc.c:571:
+		intel_engine_dump( engine, &p, "%s\n", engine->name);

total: 1 errors, 0 warnings, 0 checks, 228 lines checked
df4b8d8c35f6 drm/i915/execlists: Try preempt-reset from hardirq timer context
d8144187ca0e drm/i915/preemption: Select timeout when scheduling
0aeab6cbe712 drm/i915: Use a preemption timeout to enforce interactivity
cd1c93c17baf drm/i915: Allow user control over preempt timeout on their important context