[Intel-gfx] [PATCH v3 2/4] drm/i915/psr: Prevent PSR exit when a non-pipe related register is written

[Rodrigo Vivi]

On Fri, Apr 20, 2018 at 03:27:56PM -0700, José Roberto de Souza wrote:
> Any write in any display register was causing HW to exit PSR,
> masking it to allow more power savings. Writes to pipe related
> registers will still cause HW to exit PSR.
> This is already masked for PSR2.
> 
> Bspec: 7721 and 8042
> 
> Cc: Rodrigo Vivi <rodrigo.vivi at intel.com>
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan at intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza at intel.com>
> ---
> 
> New patch in this series.
> 
>  drivers/gpu/drm/i915/intel_psr.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index 0938df48107a..c907282dc82d 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -712,7 +712,8 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp,
>  		I915_WRITE(EDP_PSR_DEBUG,
>  			   EDP_PSR_DEBUG_MASK_MEMUP |
>  			   EDP_PSR_DEBUG_MASK_HPD |
> -			   EDP_PSR_DEBUG_MASK_LPSP);
> +			   EDP_PSR_DEBUG_MASK_LPSP |
> +			   EDP_PSR_DEBUG_MASK_DISP_REG_WRITE);

What about only setting this bit before debugfs reads
and unseting it after that?


>  	}
>  }
>  
> -- 
> 2.17.0
>