[Intel-gfx] [PATCH] drm/i95: Mark GGTT as incoherent for gen10+

[Chris Wilson]

The evidence suggests that we need to start treating writes via GGTT as
incoherent for gen10+, that is that they are internally buffered and not
immediately visible via a read along a different physical path.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107398
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107400
Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala at linux.intel.com>
---
 drivers/gpu/drm/i915/i915_pci.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index e443fe44da3a..adf80563d0a1 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -590,6 +590,7 @@ static const struct intel_device_info intel_coffeelake_gt3_info = {
 	GEN9_FEATURES, \
 	GEN(10), \
 	.ddb_size = 1024, \
+	.has_coherent_ggtt = false, \
 	GLK_COLORS
 
 static const struct intel_device_info intel_cannonlake_info = {
-- 
2.18.0