[Intel-gfx] [PATCH 21/23] drm/i915/icl: Add Display Stream Splitter control registers

[Madhav Chauhan]

On 7/31/2018 7:43 AM, Manasi Navare wrote:
> From: "Srivatsa, Anusha" <anusha.srivatsa at intel.com>
>
> Add defines for DSS_CTL registers.
> These registers specify the big joiner, splitter,
> overlap pixels and info regarding display stream
> compression enabled on left or right branch.
>
> v2:
> - Add define to conditionally check the buffer target depth (James Ausmus)
>
> Suggested-by: Madhav Chauhan <madhav.chauhan at intel.com>
> Cc: Madhav Chauhan <madhav.chauhan at intel.com>
> Cc: Manasi Navare <manasi.d.navare at intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi at intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa at intel.com>
> ---
>   drivers/gpu/drm/i915/i915_reg.h | 33 +++++++++++++++++++++++++++++++++
>   1 file changed, 33 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index b8e41db..0ae38b6 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7792,6 +7792,39 @@ enum {
>   #define RC_MAX_QP_SHIFT				5
>   #define RC_MIN_QP_SHIFT				0
>   
> +/* Display Stream Splitter Control */
> +#define DSS_CTL1				_MMIO(0x67400)
> +#define  SPLITTER_ENABLE			(1 << 31)
> +#define  JOINER_ENABLE				(1 << 30)
> +#define  DUAL_LINK_MODE_INTERLEAVE		(1 << 24)
> +#define  DUAL_LINK_MODE_FRONTBACK		(0 << 24)
> +#define  OVERLAP_PIXELS_MASK			(0xf << 16)
> +#define  OVERLAP_PIXELS(pixels)			((pixels) << 16)
> +#define  LEFT_DL_BUF_TARGET_DEPTH_MASK		(0xfff << 0)
> +#define  LEFT_DL_BUF_TARGET_DEPTH(pixels)	((pixels) << 0)
> +#define  MAX_DL_BUFFER_TARGET_DEPTH		0x5A0

Please use lower case for hex values. With this fix,
Reviewed-by: Madhav Chauhan <madhav.chauhan at intel.com>

Regards,
Madhav

> +
> +#define DSS_CTL2				_MMIO(0x67404)
> +#define  LEFT_BRANCH_VDSC_ENABLE		(1 << 31)
> +#define  RIGHT_BRANCH_VDSC_ENABLE		(1 << 15)
> +#define  RIGHT_DL_BUF_TARGET_DEPTH_MASK		(0xfff << 0)
> +#define  RIGHT_DL_BUF_TARGET_DEPTH(pixels)	((pixels) << 0)
> +
> +#define _ICL_PIPE_DSS_CTL1_PB			0x78200
> +#define _ICL_PIPE_DSS_CTL1_PC			0x78400
> +#define ICL_PIPE_DSS_CTL1(pipe)			_MMIO_PIPE((pipe) - PIPE_B, \
> +							   _ICL_PIPE_DSS_CTL1_PB, \
> +							   _ICL_PIPE_DSS_CTL1_PC)
> +#define  BIG_JOINER_ENABLE			(1 << 29)
> +#define  MASTER_BIG_JOINER_ENABLE		(1 << 28)
> +#define  VGA_CENTERING_ENABLE			(1 << 27)
> +
> +#define _ICL_PIPE_DSS_CTL2_PB			0x78204
> +#define _ICL_PIPE_DSS_CTL2_PC			0x78404
> +#define ICL_PIPE_DSS_CTL2(pipe)			_MMIO_PIPE((pipe) - PIPE_B, \
> +							   _ICL_PIPE_DSS_CTL2_PB, \
> +							   _ICL_PIPE_DSS_CTL2_PC)
> +
>   #define DSCA_RC_RANGE_PARAMETERS_1		_MMIO(0x6B248)
>   #define DSCA_RC_RANGE_PARAMETERS_1_UDW		_MMIO(0x6B248 + 4)
>   #define DSCC_RC_RANGE_PARAMETERS_1		_MMIO(0x6BA48)