[Intel-gfx] [PATCH] Revert "drm/i915/icl: WaEnableFloatBlendOptimization"

[Anuj Phogat]

On Mon, Aug 6, 2018 at 9:14 AM Chris Wilson <chris at chris-wilson.co.uk>
wrote:

> Quoting Anuj Phogat (2018-08-03 20:24:09)
> >
> >
> > On Mon, Jul 30, 2018 at 5:07 AM Mika Kuoppala <
> mika.kuoppala at linux.intel.com>
> > wrote:
> >
> >     The register for 0xe420 is unable to hold any value, including
> >     this bit. The documentation is also mixed between having a
> >     register bit for toggle and having a state command setup
> >     for it. Apparently the register toggle is deprecated.
> >
> >
> >   CACHE_MODE_SS is not listed in
> > a
> > gfxspecs table
> > which lists all
> > user mode
> >   non-privileged registers. So,
> > do you think
> > making any changes
> > to the register
> >   from mesa will hold?
>
> No, a privileged write to the register from inside the ring didn't
> stick, so something is amiss.
>
ok. Mika's commit message confused me where he mentioned
about adding back the state
setup for this bit in mesa.
But, as
I understand now the changes won't stick in the register. So,
no changes required  in mesa.

-Chris
>
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