[Intel-gfx] [PATCH 2/3] drm/i915: Unmask user interrupts writes into HWSP on snb/ivb/vlv/hsw

[Mika Kuoppala]

Chris Wilson <chris at chris-wilson.co.uk> writes:

> An oddity occurs on Sandybridge, Ivybridge and Haswell (and presumably
> Valleyview) in that for the period following the GPU restart after a
> reset, there are no GT interrupts received. From Ville's notes, bit 0 in
> the HWSTAM corresponds to the render interrupt, and if we unmask it we
> do see immediate resumption of GT interrupt delivery (via the master irq
> handler) after the reset.
>
> v2: Limit the w/a to the render interrupt from rcs
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107500
> Fixes: c5498089463b ("drm/i915: Mask everything in ring HWSTAM on gen6+ in ringbuffer mode")
> References: d420a50c21ef ("drm/i915: Clean up the HWSTAM mess")
> Testcase: igt/gem_eio/reset-stress
> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> Cc: Ville Syrjälä <ville.syrjala at linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_ringbuffer.c | 14 ++++++++++++--
>  1 file changed, 12 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 8003cef767ba..5a2601a4d1aa 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -387,8 +387,18 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
>  		mmio = RING_HWS_PGA(engine->mmio_base);
>  	}
>  
> -	if (INTEL_GEN(dev_priv) >= 6)
> -		I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff);
> +	if (INTEL_GEN(dev_priv) >= 6) {
> +		u32 mask = ~0u;
> +
> +		/*
> +		 * Keep the render interrupt unmasked as this papaers over

papers, tho papaers sounds like it needs grown up to walk it across
the reset.

> +		 * lost interrupts following a reset.
> +		 */
> +		if (engine->id == RCS)
> +			mask &= ~BIT(0);
> +
> +		I915_WRITE(RING_HWSTAM(engine->mmio_base), mask);

This is fine too as the improved test pushes it with all engines.

Acked-by: Mika Kuoppala <mika.kuoppala at linux.intel.com>

> +	}
>  
>  	I915_WRITE(mmio, engine->status_page.ggtt_offset);
>  	POSTING_READ(mmio);
> -- 
> 2.18.0
>
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