[Intel-gfx] [PATCH 01/12] drm/i915/icl: Define utility pin ctrl register bits

[Madhav Chauhan]

This patch defines utility pin control register bitfields
for ICL platform and also re-arrange existing definition to
align with guideline.

Signed-off-by: Madhav Chauhan <madhav.chauhan at intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 22 ++++++++++++++--------
 1 file changed, 14 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 77b38fe..6c863d8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4910,14 +4910,20 @@ enum {
 #define   BLM_PCH_POLARITY			(1 << 29)
 #define BLC_PWM_PCH_CTL2	_MMIO(0xc8254)
 
-#define UTIL_PIN_CTL		_MMIO(0x48400)
-#define   UTIL_PIN_ENABLE	(1 << 31)
-
-#define   UTIL_PIN_PIPE(x)     ((x) << 29)
-#define   UTIL_PIN_PIPE_MASK   (3 << 29)
-#define   UTIL_PIN_MODE_PWM    (1 << 24)
-#define   UTIL_PIN_MODE_MASK   (0xf << 24)
-#define   UTIL_PIN_POLARITY    (1 << 22)
+#define UTIL_PIN_CTL			_MMIO(0x48400)
+#define  UTIL_PIN_ENABLE		(1 << 31)
+#define  UTIL_PIN_PIPE_MASK		(3 << 29)
+#define  UTIL_PIN_PIPE(x)		((x) << 29)
+#define  UTIL_PIN_MODE_MASK		(0xf << 24)
+#define  UTIL_PIN_MODE_DATA		(0 << 24)
+#define  UTIL_PIN_MODE_PWM		(1 << 24)
+#define  UTIL_PIN_MODE_VBLANK		(4 << 24)
+#define  UTIL_PIN_MODE_VSYNC		(5 << 24)
+#define  UTIL_PIN_MODE_EYE_LEVEL	(8 << 24)
+#define  UTIL_PIN_OP_DATA		(1 << 23)
+#define  UTIL_PIN_POLARITY		(1 << 22)
+#define  ICL_UTIL_PIN_DIRECTION		(1 << 19)
+#define  ICL_UTIL_PIN_IP_DATA		(1 << 16)
 
 /* BXT backlight register definition. */
 #define _BXT_BLC_PWM_CTL1			0xC8250
-- 
2.7.4