[Intel-gfx] [PATCH 03/12] drm/i915/icl: Define DSI cmd mode registers

[Madhav Chauhan]

This patch adds definition of registers required for
DSI command mode operation.

Signed-off-by: Madhav Chauhan <madhav.chauhan at intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 51 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 51 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6c863d8..81dc656 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10535,6 +10535,57 @@ enum skl_power_gate {
 #define  LINK_ULPS_TYPE_LP11		(1 << 8)
 #define  LINK_ENTER_ULPS		(1 << 0)
 
+#define _DSI_INTR_MASK_REG_0		0x6b070
+#define _DSI_INTR_MASK_REG_1		0x6b870
+#define DSI_INTR_MASK_REG(tc)		_MMIO_DSI(tc,	\
+						  _DSI_INTR_MASK_REG_0,\
+						  _DSI_INTR_MASK_REG_1)
+
+#define _DSI_INTR_IDENT_REG_0		0x6b074
+#define _DSI_INTR_IDENT_REG_1		0x6b874
+#define DSI_INTR_IDENT_REG(tc)		_MMIO_DSI(tc,	\
+						  _DSI_INTR_IDENT_REG_0,\
+						  _DSI_INTR_IDENT_REG_1)
+#define  TE_EVENT				(1 << 31)
+#define  RX_DATA_OR_BTA_TERMINATED		(1 << 30)
+#define  TX_DATA				(1 << 29)
+#define  ULPS_ENTRY_DONE			(1 << 28)
+#define  NON_TE_TRIGGER_RECEIVED		(1 << 27)
+#define  HOST_CHKSUM_ERROR			(1 << 26)
+#define  HOST_MULTI_ECC_ERROR			(1 << 25)
+#define  HOST_SINGL_ECC_ERROR			(1 << 24)
+#define  HOST_CONTENTION_DETECTED		(1 << 23)
+#define  HOST_FALSE_CONTROL_ERROR		(1 << 22)
+#define  HOST_TIMEOUT_ERROR			(1 << 21)
+#define  HOST_LOW_POWER_TX_SYNC_ERROR		(1 << 20)
+#define  HOST_ESCAPE_MODE_ENTRY_ERROR		(1 << 19)
+#define  FRAME_UPDATE_DONE			(1 << 16)
+#define  PROTOCOL_VIOLATION_REPORTED		(1 << 15)
+#define  INVALID_TX_LENGTH			(1 << 13)
+#define  INVALID_VC				(1 << 12)
+#define  INVALID_DATA_TYPE			(1 << 11)
+#define  PERIPHERAL_CHKSUM_ERROR		(1 << 10)
+#define  PERIPHERAL_MULTI_ECC_ERROR		(1 << 9)
+#define  PERIPHERAL_SINGLE_ECC_ERROR		(1 << 8)
+#define  PERIPHERAL_CONTENTION_DETECTED		(1 << 7)
+#define  PERIPHERAL_FALSE_CTRL_ERROR		(1 << 6)
+#define  PERIPHERAL_TIMEOUT_ERROR		(1 << 5)
+#define  PERIPHERAL_LP_TX_SYNC_ERROR		(1 << 4)
+#define  PERIPHERAL_ESC_MODE_ENTRY_CMD_ERROR	(1 << 3)
+#define  EOT_SYNC_ERROR				(1 << 2)
+#define  SOT_SYNC_ERROR				(1 << 1)
+#define  SOT_ERROR				(1 << 0)
+
+#define _DSI_CMD_FRMCTL_0		0x6b034
+#define _DSI_CMD_FRMCTL_1		0x6b834
+#define DSI_CMD_FRMCTL(tc)		_MMIO_DSI(tc,	\
+						  _DSI_CMD_FRMCTL_0,\
+						  _DSI_CMD_FRMCTL_1)
+#define  FRAME_UPDATE_REQ_PRESENT	(1 << 31)
+#define  PERIODIC_FRAME_UPDATE_ENABLE	(1 << 29)
+#define  NULL_PACKET_ENABLE		(1 << 28)
+#define  FRAME_IN_PROGRESS		(1 << 0)
+
 /* DSI timeout registers */
 #define _DSI_HSTX_TO_0			0x6b044
 #define _DSI_HSTX_TO_1			0x6b844
-- 
2.7.4