[Intel-gfx] [PATCH 16/20] drm/i915: Do not initialize display clocks when display is disabled

[José Roberto de Souza]

cdclk and rawclk are the 2 display clocks that can now be completed
not initialized when display is disabled.

Signed-off-by: José Roberto de Souza <jose.souza at intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c         | 9 ++++++---
 drivers/gpu/drm/i915/intel_runtime_pm.c | 3 +++
 2 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 7e948bf30cdd..743b03d50abb 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -918,7 +918,8 @@ static int i915_driver_init_early(struct drm_i915_private *dev_priv,
 		goto err_uc;
 	intel_irq_init(dev_priv);
 	intel_hangcheck_init(dev_priv);
-	intel_init_display_hooks(dev_priv);
+	if (INTEL_INFO(dev_priv)->num_pipes)
+		intel_init_display_hooks(dev_priv);
 	intel_init_clock_gating_hooks(dev_priv);
 	if (INTEL_INFO(dev_priv)->num_pipes) {
 		intel_init_audio_hooks(dev_priv);
@@ -1390,7 +1391,8 @@ int i915_driver_load(struct pci_dev *pdev, const struct pci_device_id *ent)
 		goto out_cleanup_mmio;
 
 	/* must happen before intel_power_domains_init_hw() on VLV/CHV */
-	intel_update_rawclk(dev_priv);
+	if (INTEL_INFO(dev_priv)->num_pipes)
+		intel_update_rawclk(dev_priv);
 
 	/* i915_gem_init() call chain will call
 	 * intel_display_power_put(i915, POWER_DOMAIN_GT_IRQ);
@@ -1800,7 +1802,8 @@ static int i915_drm_resume(struct drm_device *dev)
 
 	i915_gem_resume(dev_priv);
 
-	intel_modeset_init_hw(dev);
+	if (INTEL_INFO(dev_priv)->num_pipes)
+		intel_modeset_init_hw(dev);
 	intel_init_clock_gating(dev_priv);
 
 	spin_lock_irq(&dev_priv->irq_lock);
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 43d7f9071ff4..01e0c8e82fcf 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -807,6 +807,9 @@ static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
 
 	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 
+	if (!INTEL_INFO(dev_priv)->num_pipes)
+		return;
+
 	dev_priv->display.get_cdclk(dev_priv, &cdclk_state);
 	/* Can't read out voltage_level so can't use intel_cdclk_changed() */
 	WARN_ON(intel_cdclk_needs_modeset(&dev_priv->cdclk.hw, &cdclk_state));
-- 
2.18.0